C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 108

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

C8051F360/1/2/3/4/5/6/7/8/9
10.2. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to
configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the
interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed prior-
ity order is used to arbitrate, given in Table 10.1.
10.3. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is
5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. Additional clock cycles will be required if a cache miss occurs (see Section 14 for more details). If an
interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to
service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other inter-
rupt is currently being serviced or the new interrupt is of greater priority) is when the CPU is performing an
RETI instruction followed by a DIV as the next instruction, and a cache miss event also occurs. If the CPU
is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until
the current ISR completes, including the RETI and following instruction.
108
Interrupt Source
Reset
External Interrupt 0 (/INT0) 0x0003
Timer 0 Overflow
External Interrupt 1 (/INT1) 0x0013
Timer 1 Overflow
UART0
Timer 2 Overflow
SPI0
SMB0
RESERVED
ADC0 Window
Comparator
ADC0 End of Conversion
Interrupt
Vector
0x0000
0x000B
0x001B
0x0023
0x002B
0x0033
0x003B
0x0043
0x004B
0x0053
Table 10.1. Interrupt Summary
Priority
Order
Top
10
0
1
2
3
4
5
6
7
8
9
Pending Flag
None
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.0)
N/A
AD0WINT
(ADC0CN.5)
AD0INT (ADC0STA.5)
Rev. 1.0
N/A N/A
N/A N/A
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
Y
Y
Y
Y
Enable
Flag
EX0 (IE.0) PX0 (IP.0)
EX1 (IE.2) PX1 (IP.2)
ES0 (IE.4) PS0 (IP.4)
ET0 (IE.1)
ET1 (IE.3)
ET2 (IE.5)
EWADC0
Enabled
(EIE1.0)
(EIE1.2)
(EIE1.3)
ESMB0
EADC0
Always
ESPI0
(IE.6)
N/A
Priority
Control
PT0 (IP.1)
PT1 (IP.3)
PT2 (IP.5)
PWADC0
(EIP1.0)
(EIP1.2)
(EIP1.3)
Highest
PSMB0
PADC0
Always
PSPI0
(IP.6)
N/A