C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 80

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

C8051F360/1/2/3/4/5/6/7/8/9
9.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
five 16-bit counter/timers (see description in Section 21), one full-duplex UART (see description in Section
19), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (see Section
9.4.6), and up to four byte-wide and one 7-bit-wide I/O Ports (see description in Section 17). The CIP-51
also includes on-chip debug hardware (see description in Section 24), and interfaces directly with the
MCU’s analog and digital subsystems providing a complete data acquisition or control-system solution in a
single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
9.1.
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's system clock running at 100 MHz, it has a peak throughput of 100 MIPS. The CIP-51
has a total of 109 instructions. The table below shows the total number of instructions that require each
execution time.
80
Number of Instructions
- Fully Compatible with MCS-51 Instruction
- 100 or 50 MIPS Peak Using the On-Chip
- 256 Bytes of Internal RAM
- 8/4 Byte-Wide I/O Ports
Clocks to Execute
Set
PLL
CIP-51 Microcontroller
Performance
26
1
50
2
2/3
Rev. 1.0
5
14
3
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
3/4
7
4
3
4/5
1
5
2
8
1