C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 133

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

Note:For bits that act as both reset source enables (on a write) and reset indicator flags (on a read),
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
SFR Page:
SFR Address:
Bit7
R
–
UNUSED. Read = 0b. Write = don’t care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0. Write: Comparator0 is not a reset
1: Read: Source of last reset was Comparator0. Write: Comparator0 is a reset source
(active-low).
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit. Write: No Effect.
1: Read: Source of last reset was a write to the SWRSF bit. Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout. Write: Missing
1: Read: Source of last reset was a Missing Clock Detector timeout. Write: Missing Clock
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the V
Monitor as a reset source. Note: writing ‘1’ to this bit before the V
and stabilized may cause a system reset. See register VDM0CN (SFR Definition 12.1)
0: Read: Last reset was not a power-on or V
1: Read: Last reset was a power-on or V
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
read-modify-write instructions read and modify the source enable only. [This applies to bits:
C0RSEF, SWRSF, MCDRSF, PORSF].
all pages
0xEF
FERROR C0RSEF
source.
Clock Detector disabled.
Detector enabled; triggers a reset if a missing clock condition is detected.
reset source.
indeterminate. Write: V
Bit6
R
SFR Definition 12.2. RSTSRC: Reset Source
R/W
Bit5
SWRSF
DD
R/W
Bit4
Monitor is a reset source.
WDTRSF MCDRSF
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
Bit3
R
DD
Monitor reset; all other reset flags
DD
Monitor reset. Write: V
R/W
Bit2
PORSF
R/W
Bit1
DD
DD
PINRSF
Monitor is enabled
Bit0
Monitor is not a
R
Reset Value
Variable
DD
133