C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 180

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

C8051F360/1/2/3/4/5/6/7/8/9
To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external
clock source, using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’.
Finally, the PLL can be powered off, by setting PLLPWR (PLL0CN.0) to ‘0’. Note that the PLLEN and PLL-
PWR bits can be cleared at the same time.
180
Bits 7–5: UNUSED. Read = 000b. Write = don’t care.
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Bits 7–5: UNUSED. Read = 000b. Write = don’t care.
Bits 4–0: PLLM4–0: PLL Reference Clock Pre-divider.
SFR Page:
SFR Address:
SFR Page:
SFR Address:
R/W
R/W
Bit7
Bit7
–
–
PLLLCK: PLL Lock Flag.
0: PLL Frequency is not locked.
1: PLL Frequency is locked.
RESERVED. Read = 0b. Must Write 0b.
PLLSRC: PLL Reference Clock Source Select Bit.
0: PLL Reference Clock Source is Internal Oscillator.
1: PLL Reference Clock Source is External Oscillator.
PLLEN: PLL Enable Bit.
0: PLL is held in reset.
1: PLL is enabled. PLLPWR must be ‘1’.
PLLPWR: PLL Power Enable.
0: PLL bias generator is de-activated. No static power is consumed.
1: PLL bias generator is active. Must be set for PLL to operate.
These bits select the pre-divide value of the PLL reference clock. When set to any non-zero
value, the reference clock will be divided by the value in PLLM4–0. When set to ‘00000b’,
the reference clock will be divided by 32.
F
0xB3
F
0xA9
R/W
R/W
Bit6
Bit6
–
–
SFR Definition 16.7. PLL0DIV: PLL Pre-divider
SFR Definition 16.6. PLL0CN: PLL Control
R/W
R/W
Bit5
Bit5
–
–
PLLLCK
PLLM4
R/W
Bit4
Bit4
R
Reserved
Rev. 1.0
PLLM3
R/W
Bit3
R/W
Bit3
PLLM2
PLLSRC
R/W
Bit2
R/W
Bit2
PLLM1
PLLEN
R/W
Bit1
R/W
Bit1
PLLM0
PLLPWR 00000000
R/W
Bit0
R/W
Bit0
00000001
Reset Value
Reset Value