MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 43

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing diagrams for FIFO appear in
Freescale Semiconductor
Rise time TX_CLK (20%–80%)
Fall time TX_CLK (80%–20%)
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
Note:
1. Data valid t
2. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
Note:
1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency
– Max Hold)
of the speed bins the part belongs to as well as the FIFO mode under operation. See
Restrictions,”
of the speed bins the part belongs to as well as the FIFO mode under operation. See
Restrictions,”
GTX_CLK
TXD[7:0]
TX_EN
TX_ER
FITDV
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
for more detailed description.
Parameter/Condition
for more detailed description.
Parameter/Condition
to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time
Table 26. FIFO Mode Transmit AC Timing Specification (continued)
1
Table 27. FIFO Mode Receive AC Timing Specification
t
FITH
Figure 14. FIFO Transmit AC Timing Diagram
Figure 14
t
FIT
and
Figure
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
t
FITDV
15.
t
FIRH
Symbol
t
t
t
t
FIRDV
FIRDX
t
t
FIRR
FIRJ
FIRF
FIR
Symbol
/t
t
FIRH
FITDX
t
t
FITR
FITF
1
t
FITDX
Min
6.0
1.5
0.5
45
—
—
—
t
Min
FITF
0.5
—
—
Typ
8.0
50
—
—
—
—
—
Section 2.4.6, “Platform to FIFO
Section 2.4.6, “Platform to FIFO
Typ
—
—
—
t
FITR
Max
0.75
0.75
100
250
55
—
—
Max
0.75
0.75
3.0
Unit
Unit
ns
ps
ns
ns
ns
ns
%
ns
ns
ns
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