MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet
MPC8536DS
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MPC8536DS Summary of contents
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MPC8536E PowerQUICC III™ Integrated Processor Reference Manual Supports MPC8536E MPC8535E MPC8536ERM Rev. 1 05/2009 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...
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... Power Management Controller.................................................................................... 1-7 1.3.9 PCI Express Controller ................................................................................................ 1-8 1.3.10 Programmable Interrupt Controller (PIC).................................................................... 1-8 1.3.11 Enhanced Secure Digital Host Controller (eSDHC).................................................... 1-8 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Contents About This Book Part I Overview Chapter 1 ...
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... General Utilities Registers ......................................................................................... 2-12 2.3.5 Interrupt Controller and CCSR .................................................................................. 2-13 2.3.6 Device-Specific Utilities............................................................................................ 2-13 2.4 Complete CCSR Map .................................................................................................... 2-14 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title 2 C, DUART, eLBC ........................................................................ 1-9 Chapter 2 Memory Map Page Number Freescale Semiconductor ...
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... Boot ROM Location .............................................................................................. 4-14 4.4.3.7 Host/Agent Configuration ..................................................................................... 4-15 4.4.3.8 SerDes1 I/O Port Selection.................................................................................... 4-16 4.4.3.9 SerDes2 I/O Port Selection.................................................................................... 4-17 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 3 Signal Descriptions Chapter 4 Reset, Clocking, and Initialization Page ...
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... Boot ROM..................................................................................................... 4-35 4.5.1.2.1 Overview ........................................................................................................... 4-35 4.5.1.2.2 Features.............................................................................................................. 4-36 4.5.1.2.3 EEPROM Data Structure................................................................................... 4-36 4.5.1.2.4 eSPI Controller Configuration........................................................................... 4-40 4.5.1.3 Default e500 Addressing During System Boot ..................................................... 4-41 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...
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... L2 Cache and SRAM Coherency................................................................................... 6-27 6.6.1 L2 Cache Coherency Rules........................................................................................ 6-28 6.6.2 Memory-Mapped SRAM Coherency Rules .............................................................. 6-29 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Part II e500 Core Complex and L2 Cache Chapter 5 e500 Core Integration Details Chapter 6 ...
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... ECM Error Attributes Capture Register (EEATR) .................................................. 7-7 7.2.1.8 ECM Error Low Address Capture Register (EELADR) ......................................... 7-8 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 viii Contents Title Part III Memory, Security, and I/O Interfaces Chapter 7 e500 Coherency Module Page Number Freescale Semiconductor ...
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... DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) ............................. 8-34 8.4.1.16 DDR Initialization Address (DDR_INIT_ADDR)................................................ 8-34 8.4.1.17 DDR Initialization Enable Extended Address (DDR_INIT_EXT_ADDR) .......... 8-35 8.4.1.18 DDR SDRAM Timing Configuration 4 (TIMING_CFG_4)................................. 8-36 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 8 DDR Memory Controller Page Number ix ...
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... DDR SDRAM Refresh and Power-Saving Modes ................................................ 8-80 8.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 8-82 8.5.9 DDR Data Beat Ordering........................................................................................... 8-83 8.5.10 Page Mode and Logical Bank Retention ................................................................... 8-83 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...
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... Spurious Vector Register (SVR)............................................................................ 9-23 9.3.2 Global Timer Registers .............................................................................................. 9-23 9.3.2.1 Timer Frequency Reporting Register (TFRRA–TFRRB) ..................................... 9-24 9.3.2.2 Global Timer Current Count Registers (GTCCRA0–GTCCRA3, GTCCRB0–GTCCRB3)..................................................................................... 9-24 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 9 Page Number xi ...
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... Who Am I Registers 0–1 (WHOAMI0–WHOAMI1) ........................................... 9-50 9.3.8.4 Processor Core Interrupt Acknowledge Registers 0–1 (IACK0–IACK1)............. 9-50 9.3.8.5 Processor Core End of Interrupt Registers (EOI0–EOI1) ..................................... 9-51 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xii Contents Title Page Number Freescale Semiconductor ...
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... Cyclical Redundancy Check Unit (CRCU) ......................................................... 10-10 10.1.4.8 Random Number Generator Unit (RNGU).......................................................... 10-11 10.2 Configuration of Internal Memory Space .................................................................... 10-11 10.3 Descriptors ................................................................................................................... 10-19 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 10 Security Engine (SEC) 3.0 Page Number xiii ...
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... System Bus Master Write—Detailed Description ........................................... 10-48 10.5.2 Arbitration Algorithms ............................................................................................ 10-48 10.5.2.1 Round-Robin Arbitration..................................................................................... 10-48 10.5.2.2 Weighted Priority Arbitration .............................................................................. 10-48 10.5.3 Controller Interrupts ................................................................................................ 10-49 10.5.3.1 Controller Interrupt Conditions and Interrupt Generation................................... 10-49 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xiv Contents Title Page Number Freescale Semiconductor ...
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... AFEU Status Register.......................................................................................... 10-91 10.7.2.6 AFEU Interrupt Status Register........................................................................... 10-92 10.7.2.7 AFEU Interrupt Mask Register............................................................................ 10-94 10.7.2.8 AFEU End of Message Register.......................................................................... 10-96 10.7.2.9 AFEU Context ..................................................................................................... 10-96 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xv ...
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... KEU Interrupt Status Register (KEUISR) ......................................................... 10-123 10.7.5.7 KEU Interrupt Mask Register (KEUIMR) ........................................................ 10-125 10.7.5.8 KEU Data Out Register (f9 MAC) (KEUDOR)................................................ 10-127 10.7.5.9 KEU End of Message Register (KEUEMR) ..................................................... 10-127 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xvi Contents Title Page Number Freescale Semiconductor ...
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... PKEU Parameter Memory N ......................................................................... 10-155 10.7.8 Random Number Generator Unit (RNGU)............................................................ 10-155 10.7.8.1 RNGU Mode Register ....................................................................................... 10-156 10.7.8.2 RNGU Data Size Register ................................................................................. 10-156 10.7.8.3 RNGU Reset Control Register........................................................................... 10-156 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xvii ...
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... Arbitration Procedure .............................................................................................. 11-15 11.4.2.1 Arbitration Control .............................................................................................. 11-15 11.4.3 Handshaking ............................................................................................................ 11-16 11.4.4 Clock Control........................................................................................................... 11-16 11.4.4.1 Clock Synchronization......................................................................................... 11-16 11.4.4.2 Input Synchronization and Digital Filter ............................................................. 11-16 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xviii Contents Title Chapter Interfaces Page Number Freescale Semiconductor ...
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... Modem Control Registers (UMCRn) .................................................................. 12-14 12.3.1.10 Line Status Registers (ULSRn) ........................................................................... 12-15 12.3.1.11 Modem Status Registers (UMSRn) ..................................................................... 12-16 12.3.1.12 Scratch Registers (USCRn) ................................................................................. 12-17 12.3.1.13 DMA Status Registers (UDSRn) ......................................................................... 12-17 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 12 DUART Page Number xix ...
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... UPM Mode Registers (MxMR) ........................................................................... 13-21 13.3.1.5 Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 13-23 13.3.1.6 UPM/FCM Data Register (MDR) ....................................................................... 13-23 13.3.1.7 Special Operation Initiation Register (LSOR)..................................................... 13-24 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title Chapter 13 Enhanced Local Bus Controller Page Number Freescale Semiconductor ...
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... FCM Buffer RAM ............................................................................................... 13-61 13.4.3.1.1 Buffer Layout and Page Mapping for Small-Page NAND Flash Devices ...... 13-61 13.4.3.1.2 Buffer Layout and Page Mapping for Large-Page NAND Flash Devices ...... 13-62 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxi ...
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... Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 13-89 13.4.4.6 Extended Hold Time on Read Accesses .............................................................. 13-90 13.5 Initialization/Application Information ......................................................................... 13-90 13.5.1 Interfacing to Peripherals in Different Address Modes ........................................... 13-90 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxii Contents Title Page Number Freescale Semiconductor ...
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... Ethernet Control Register (ECNTRL) ............................................................. 14-35 14.5.3.1.7 Pause Time Value Register (PTV) ................................................................... 14-37 14.5.3.1.8 DMA Control Register (DMACTRL) ............................................................. 14-38 14.5.3.1.9 TBI Physical Address Register (TBIPA) ......................................................... 14-40 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 14 Page Number xxiii ...
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... MAC Configuration 1 Register (MACCFG1)................................................. 14-74 14.5.3.5.2 MAC Configuration 2 Register (MACCFG2)................................................. 14-76 14.5.3.5.3 Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) ................................... 14-78 14.5.3.5.4 Half-Duplex Register (HAFDUP) ................................................................... 14-79 14.5.3.5.5 Maximum Frame Length Register (MAXFRM) ............................................. 14-80 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxiv Contents Title Page Number Freescale Semiconductor ...
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... Receive Fragments Counter (RFRG) .............................................................. 14-98 14.5.3.6.23 Receive Jabber Counter (RJBR)...................................................................... 14-99 14.5.3.6.24 Receive Dropped Packet Counter (RDRP)...................................................... 14-99 14.5.3.6.25 Transmit Byte Counter (TBYT) .................................................................... 14-100 14.5.3.6.26 Transmit Packet Counter (TPKT).................................................................. 14-100 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxv ...
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... Timer Event Mask Register (TMR_TEMASK) ............................................ 14-125 14.5.3.11.4 Timer PTP Packet Event Register (TMR_PEVENT) .................................... 14-126 14.5.3.11.5 Timer Event Mask Register (TMR_PEMASK) ............................................ 14-127 14.5.3.11.6 Timer Status Register (TMR_STAT) ............................................................. 14-128 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxvi Contents Title Page Number Freescale Semiconductor ...
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... SGMII Interface................................................................................................. 14-156 14.6.2 Connecting to FIFO Interfaces .............................................................................. 14-156 14.6.2.1 Flow Control...................................................................................................... 14-157 14.6.2.2 CRC Appending and Checking ......................................................................... 14-157 14.6.2.3 8-Bit GMII-Style Packet FIFO Mode................................................................ 14-158 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxvii ...
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... Filer Example—802.1p Priority Filing.......................................................... 14-187 14.6.5.2.7 Filer Example—IP Diff-Serv Code Points Filing.......................................... 14-188 14.6.5.2.8 Filer Example—TCP and UDP Port Filing .................................................. 14-188 14.6.5.3 Transmission Scheduling................................................................................... 14-189 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxviii Contents Title Page Number Freescale Semiconductor ...
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... FIFO Mode ............................................................................................... 14-232 14.7.1.8 SGMII Interface Support ................................................................................... 14-234 15.1 Introduction.................................................................................................................... 15-1 15.1.1 Block Diagram........................................................................................................... 15-1 15.1.2 Overview.................................................................................................................... 15-2 15.1.3 Features...................................................................................................................... 15-2 15.1.4 Modes of Operation ................................................................................................... 15-2 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 15 DMA Controller Page Number xxix ...
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... Channel Abort...................................................................................................... 15-31 15.4.1.6 Bandwidth Control............................................................................................... 15-31 15.4.1.7 Channel State ....................................................................................................... 15-31 15.4.1.8 Illustration of Stride Size and Stride Distance..................................................... 15-32 15.4.2 DMA Transfer Interfaces ......................................................................................... 15-32 15.4.3 DMA Errors ............................................................................................................. 15-32 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxx Contents Title Page Number Freescale Semiconductor ...
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... PCI ATMU Inbound Registers............................................................................. 16-19 16.3.1.3.1 PCI Inbound Translation Address Registers (PITARn)................................... 16-20 16.3.1.3.2 PCI Inbound Window Base Address Registers (PIWBARn) .......................... 16-20 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title C ......................................................................................................... 15-39 Chapter 16 PCI Bus Interface Page ...
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... PCI Bus Arbitration ................................................................................................. 16-42 16.4.1.1 PCI Bus Arbiter Operation .................................................................................. 16-43 16.4.1.2 PCI Bus Parking .................................................................................................. 16-44 16.4.1.3 Broken Master Lock-Out ..................................................................................... 16-44 16.4.1.4 Power-Saving Modes and the PCI Arbiter .......................................................... 16-45 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxxii Contents Title Page Number Freescale Semiconductor ...
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... Agent Mode ......................................................................................................... 16-68 16.5.1.3 Agent Configuration Lock Mode......................................................................... 16-68 16.5.2 Byte Ordering .......................................................................................................... 16-69 16.5.2.1 Byte Order for Configuration Transactions ......................................................... 16-70 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 17 PCI Express Interface Controller Page Number xxxiii ...
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... PCI Express Inbound ATMU Registers ............................................................... 17-25 17.3.5.2.1 EP Inbound ATMU Implementation................................................................ 17-25 17.3.5.2.2 RC Inbound ATMU Implementation ............................................................... 17-25 17.3.5.2.3 PCI Express Inbound Translation Address Registers (PEXITARn)................ 17-26 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxxiv Contents Title Page Number Freescale Semiconductor ...
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... PCI Express BIST Register—0x0F ................................................................. 17-51 17.3.8.2 Type 0 Configuration Header .............................................................................. 17-51 17.3.8.2.1 PCI Express Base Address Registers—0x10–0x27......................................... 17-51 17.3.8.2.2 PCI Express Subsystem Vendor ID Register (EP-Mode Only)—0x2C .......... 17-54 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxv ...
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... PCI Express Link Capabilities Register—0x58 .................................................. 17-74 17.3.9.11 PCI Express Link Control Register—0x5C......................................................... 17-74 17.3.9.12 PCI Express Link Status Register—0x5E ........................................................... 17-75 17.3.9.13 PCI Express Slot Capabilities Register—0x60.................................................... 17-76 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxxvi Contents Title Page Number Freescale Semiconductor ...
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... Byte Order for Configuration Transactions ................................................... 17-101 17.4.1.3 Lane Reversal .................................................................................................... 17-101 17.4.1.4 Transaction Ordering Rules ............................................................................... 17-102 17.4.1.5 Memory Space Addressing................................................................................ 17-102 17.4.1.6 I/O Space Addressing ........................................................................................ 17-102 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxvii ...
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... Memory Map/Register Definition ................................................................................. 18-5 18.3.1 Register Descriptions................................................................................................. 18-6 18.3.1.1 eSPI Mode Register (SPMODE) ........................................................................... 18-6 18.3.1.2 eSPI Event Register (SPIE) ................................................................................... 18-6 18.3.1.3 eSPI Mask Register (SPIM)................................................................................... 18-7 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxxviii Contents Title Chapter 18 Page Number Freescale Semiconductor ...
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... SATA Interface Status Register (SStatus)............................................................ 19-15 19.3.3.2 SATA Interface Error Register (SError) .............................................................. 19-16 19.3.3.3 SATA Interface Control Register (SControl)....................................................... 19-18 19.3.3.4 SATA Interface Notification Register (SNotification)......................................... 19-19 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 19 SATA Controller Page Number xxxix ...
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... Debug Functionality ............................................................................................ 19-40 19.5.1.11 BIST Support ....................................................................................................... 19-41 19.6 PHY Control Layer Overview ..................................................................................... 19-41 19.7 Initialization/Application Information ......................................................................... 19-41 19.7.1 SATA Controller Initialization Steps ....................................................................... 19-41 Enhanced Secure Digital Host Controller MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title Chapter 20 Page Number Freescale Semiconductor ...
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... Data Agent ........................................................................................................... 20-42 20.5.4 Clock & Reset Manager........................................................................................... 20-42 20.5.5 Clock Generator....................................................................................................... 20-43 20.5.6 Card Insertion and Removal Detection.................................................................... 20-43 20.5.7 Power Management and Wake-Up Events .............................................................. 20-43 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xli ...
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... Memory Map/Register Definitions ................................................................................ 21-4 21.3.1 Capability Registers................................................................................................... 21-6 21.3.1.1 Capability Registers Length (CAPLENGTH) ....................................................... 21-7 21.3.1.2 Host Controller Interface Version (HCIVERSION) .............................................. 21-7 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xlii Contents Title Chapter 21 Universal Serial Bus Interfaces Page Number Freescale Semiconductor ...
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... PHY Interface .......................................................................................................... 21-41 21.5 Host Data Structures .................................................................................................... 21-41 21.5.1 Periodic Frame List.................................................................................................. 21-42 21.5.2 Asynchronous List Queue Head Pointer.................................................................. 21-43 21.5.3 Isochronous (High-Speed) Transfer Descriptor (iTD)............................................. 21-44 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xliii ...
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... Empty Asynchronous Schedule Detection .......................................................... 21-78 21.6.9.4 Asynchronous Schedule Traversal: Start Event................................................... 21-79 21.6.9.5 Reclamation Status Bit (USBSTS Register)........................................................ 21-79 21.6.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads................................ 21-79 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xliv Contents Title Page Number Freescale Semiconductor ...
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... Port Change Events ....................................................................................... 21-115 21.6.14.2.2 Frame List Rollover....................................................................................... 21-115 21.6.14.2.3 Interrupt on Async Advance.......................................................................... 21-115 21.6.14.2.4 Host System Error ......................................................................................... 21-116 21.7 Device Data Structures .............................................................................................. 21-116 21.7.1 Endpoint Queue Head............................................................................................ 21-117 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xlv ...
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... Managing Transfers with Transfer Descriptors ..................................................... 21-138 21.8.5.1 Software Link Pointers ...................................................................................... 21-138 21.8.5.2 Building a Transfer Descriptor .......................................................................... 21-138 21.8.5.3 Executing a Transfer Descriptor ........................................................................ 21-139 21.8.5.4 Transfer Completion .......................................................................................... 21-139 21.8.5.5 Flushing/De-Priming an Endpoint ..................................................................... 21-140 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xlvi Contents Title Page Number Freescale Semiconductor ...
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... Memory Map/Register Definition ................................................................................. 22-2 22.3.1 GPIO Direction Register (GPDIR) ............................................................................ 22-2 22.3.2 GPIO Open Drain Register (GPODR)....................................................................... 22-3 22.3.3 GPIO Data Register (GPDAT)................................................................................... 22-3 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 22 General Purpose I/O (GPIO) Page Number xlvii ...
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... Reset Request Status and Control Register (RSTRSCR) .................................... 23-27 23.4.1.18 Exception Reset Control Register (ECTRSTCR)................................................ 23-28 23.4.1.19 Automatic Reset Status Register (AUTORSTSR)............................................... 23-28 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xlviii Contents Title Part IV Global Functions and Debug Chapter 23 Global Utilities Page Number Freescale Semiconductor ...
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... Requirements for Reaching and Recovering from Deep Sleep State .................. 23-56 23.5.1.14 Requirements for Generating Wake-Up Events................................................... 23-57 23.5.1.14.1 USB ................................................................................................................. 23-57 23.5.1.14.2 GPIO ................................................................................................................ 23-58 23.5.1.14.3 Timer................................................................................................................ 23-58 23.5.1.14.4 eTSEC Wake-on LAN—Magic Packet ........................................................... 23-58 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xlix ...
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... Overview.................................................................................................................... 25-1 25.1.2 Features...................................................................................................................... 25-3 25.1.3 Modes of Operation ................................................................................................... 25-3 25.1.3.1 Local Bus (LBC) Debug Mode.............................................................................. 25-4 25.1.3.2 DDR SDRAM Interface Debug Modes ................................................................. 25-4 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title Chapter 24 Device Performance Monitor Chapter 25 Page Number Freescale Semiconductor ...
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... Local Bus Interface Debug ...................................................................................... 25-26 25.4.4 Watchpoint Monitor ................................................................................................. 25-26 25.4.4.1 Watchpoint Monitor Performance Monitor Events ............................................. 25-26 25.4.5 Trace Buffer ............................................................................................................. 25-27 25.4.5.1 Traced Data Formats (as a Function of TBCR1[IFSEL]).................................... 25-27 25.5 Initialization ................................................................................................................. 25-30 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number li ...
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... Watchpoint Monitor and Trace Buffer...................................................................... A-51 B.1 Changes From Revision 0 to Revision 1 .........................................................................B-1 C.1 Overview of Differences..................................................................................................C-1 C.2 Signal Differences............................................................................................................C-2 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lii Contents Title Appendix A Appendix B Revision History Appendix C MPC8535E Page Number Freescale Semiconductor ...
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... SerDes2 (SATA) I/O Port Selection.........................................................................C-5 C.4 Differences in Peripheral Blocks .....................................................................................C-5 C.4.1 PCI Express Interfaces.................................................................................................C-5 C.4.2 USB Controllers...........................................................................................................C-5 C.4.3 SATA Controllers.........................................................................................................C-6 C.4.4 eTSEC Controllers.......................................................................................................C-6 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number liii ...
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... Paragraph Number MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 liv Contents Title Page Number Freescale Semiconductor ...
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... Physical Address Usage for L2 Cache Accesses .................................................................... 6-5 6-4 Physical Address Usage for SRAM Accesses ........................................................................ 6-6 6-5 Data Bus Connection of CCB ................................................................................................. 6-8 6-6 Address Bus Connection of CCB............................................................................................ 6-8 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Figures Page Number lv ...
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... DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) ................................................ 8-19 8-8 DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2).................................. 8-21 8-9 DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) .............................. 8-23 8-10 DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)....................... 8-26 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lvi Figures Title Page Number Freescale Semiconductor ...
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... Example 256-Mbyte DDR SDRAM Configuration With ECC ............................................ 8-63 8-49 DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 8-74 8-50 DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTOR ............................... 8-75 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lvii ...
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... Message Enable Register (MER) .......................................................................................... 9-35 9-30 Message Status Register (MSR)............................................................................................ 9-36 9-31 Message Signaled Interrupt Registers (MSIRn) ................................................................... 9-37 9-32 Shared Message Signaled Interrupt Status Register (MSISR).............................................. 9-37 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lviii Figures Title Page Number Freescale Semiconductor ...
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... IP Block Revision Register ................................................................................................. 10-54 10-20 Master Control Register ...................................................................................................... 10-55 10-21 AESU Mode Register.......................................................................................................... 10-58 10-22 AESU Key Size Register .................................................................................................... 10-61 10-23 AESU Data Size Register ................................................................................................... 10-61 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lix ...
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... DEU Status Register ......................................................................................................... 10-112 10-61 DEU Interrupt Status Register .......................................................................................... 10-113 10-62 DEU Interrupt Mask Register ........................................................................................... 10-115 10-63 DEU End of Message Register ......................................................................................... 10-116 10-64 KEU Mode Register.......................................................................................................... 10-118 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Figures Title Page Number Freescale Semiconductor ...
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... PKEU Interrupt Mask Register ......................................................................................... 10-153 10-102 PKEU End of Message Register ....................................................................................... 10-154 10-103 RNGU Mode Register....................................................................................................... 10-156 10-104 RNGU Data Size Register................................................................................................. 10-156 10-105 RNGU Reset Control Register.......................................................................................... 10-156 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxi ...
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... UPM Mode Registers (MxMR)........................................................................................... 13-21 13-8 Memory Refresh Timer Prescaler Register (MRTPR)........................................................ 13-23 13-9 UPM Data Register in UPM Mode (MDR) ........................................................................ 13-24 13-10 FCM Data Register in FCM Mode (MDR)......................................................................... 13-24 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxii Figures Title Page Number Freescale Semiconductor ...
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... GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) ......................... 13-57 13-44 GPCM Read Followed by Write (TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads) ............................ 13-57 13-45 External Termination of GPCM Access.............................................................................. 13-58 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxiii ...
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... Single-Beat Write Access to FPM DRAM ....................................................................... 13-101 13-78 Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown)............................ 13-102 13-79 Refresh Cycle (CBR) to FPM DRAM .............................................................................. 13-103 13-80 Exception Cycle ................................................................................................................ 13-104 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxiv Figures Title Page Number Freescale Semiconductor ...
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... RBPTR0–RBPTR7 Register Definition .............................................................................. 14-69 14-36 RBASEH Register Definition ............................................................................................. 14-70 14-37 RBASE Register Definition ................................................................................................ 14-70 14-38 TMR_RXTS_H/L Register Definition................................................................................ 14-71 14-39 MACCFG1 Register Definition .......................................................................................... 14-74 14-40 MACCFG2 Register Definition .......................................................................................... 14-76 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxv ...
Page 66
... Receive Dropped Packet Counter Register Definition ....................................................... 14-99 14-79 Transmit Byte Counter Register Definition ...................................................................... 14-100 14-80 Transmit Packet Counter Register Definition ................................................................... 14-100 14-81 Transmit Multicast Packet Counter Register Definition ................................................... 14-101 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxvi Figures Title Page Number Freescale Semiconductor ...
Page 67
... TMR_PRSC Register Definition ...................................................................................... 14-130 14-118 TMROFF_H/L Register Definition .................................................................................. 14-131 14-119 TMR_ALARM1-2_H/L Register Definition .................................................................... 14-131 14-120 TMR_FIPERn Register Definition ................................................................................... 14-133 14-121 TMR_ETTS1-2_H/L Register Definition ......................................................................... 14-133 14-122 Control Register Definition............................................................................................... 14-136 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxvii ...
Page 68
... Mapping of RxBDs Data Structure ........................................................................ 14-206 15-1 DMA Block Diagram............................................................................................................ 15-1 15-2 DMA Operational Flow Chart .............................................................................................. 15-4 15-3 DMA Signal Summary.......................................................................................................... 15-4 15-4 DMA Mode Registers (MRn) ............................................................................................... 15-9 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxviii Figures Title Page Number Freescale Semiconductor ...
Page 69
... PCI Inbound Window Attributes Registers......................................................................... 16-21 16-15 PCI Error Detect Register (ERR_DR) ................................................................................ 16-24 16-16 PCI Error Capture Disable Register (ERR_CAP_DR) ....................................................... 16-25 16-17 PCI Error Enable Register (ERR_EN)................................................................................ 16-26 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxix ...
Page 70
... DAC Single-Beat Read Example........................................................................................ 16-57 16-55 DAC Burst Read Example .................................................................................................. 16-57 16-56 DAC Single-Beat Write Example ....................................................................................... 16-58 16-57 DAC Burst Write Example ................................................................................................. 16-58 16-58 Standard PCI Configuration Header ................................................................................... 16-59 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxx Figures Title Page Number Freescale Semiconductor ...
Page 71
... Internal Source, Outbound Transaction.......................................................................... 17-37 17-29 PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0) External Source, Inbound Transaction ........................................................................... 17-37 17-30 PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1) Internal Source, Outbound Transaction.......................................................................... 17-38 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxxi ...
Page 72
... PCI Express I/O Base Register ........................................................................................... 17-60 17-64 PCI Express I/O Limit Register .......................................................................................... 17-60 17-65 PCI Express Secondary Status Register.............................................................................. 17-61 17-66 PCI Express Memory Base Register ................................................................................... 17-62 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxii Figures Title Page Number Freescale Semiconductor ...
Page 73
... PCI Express Uncorrectable Error Mask Register ............................................................... 17-84 17-105 PCI Express Uncorrectable Error Severity Register ........................................................... 17-85 17-106 PCI Express Correctable Error Status Register................................................................... 17-86 17-107 PCI Express Correctable Error Mask Register ................................................................... 17-86 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxxiii ...
Page 74
... SPITF Example—SPMODEx[REVx]=1, SPMODEx[LENx]=15, MSB Sent First .......... 18-11 18-13 eSPI Receive Data Register (SPIRF) .................................................................................. 18-11 18-14 SPIRF Example—SPMODEx[LENx]=3............................................................................ 18-11 18-15 SPIRF Example—SPMODEx[LENx]=10.......................................................................... 18-11 18-16 SPIRF Example—SPMODEx[LENx]=15.......................................................................... 18-11 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxiv Figures Title Page Number Freescale Semiconductor ...
Page 75
... System Connection of the eSDHC........................................................................................ 20-1 20-2 eSDHC Block Diagram......................................................................................................... 20-2 20-3 DMA System Address Register (DSADDR) ........................................................................ 20-6 20-4 Block Attributes Register (BLKATTR) ................................................................................ 20-6 20-5 Command Argument Register (CMDARG) ......................................................................... 20-7 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxxv ...
Page 76
... Transmit FIFO Tuning Controls (TXFILLTUNING) ......................................................... 21-22 21-18 ULPI Register Access (ULPI VIEWPORT) ....................................................................... 21-23 21-19 Configure Flag Register (CONFIGFLAG) ......................................................................... 21-24 21-20 Port Status and Control (PORTSC)..................................................................................... 21-25 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxvi Figures Title Page Number Freescale Semiconductor ...
Page 77
... Split Transaction State Machine for Isochronous ............................................................. 21-104 21-59 End Point Queue Head Organization ................................................................................ 21-117 21-60 Endpoint Queue Head Layout........................................................................................... 21-118 21-61 Endpoint Transfer Descriptor (dTD)................................................................................. 21-120 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxxvii ...
Page 78
... System Version Register (SVR).......................................................................................... 23-30 23-22 Reset Control Register (RSTCR)........................................................................................ 23-30 23-23 LBC Voltage Select Control Register (LBCVSELCR)....................................................... 23-31 23-24 DDR Clock Disable Register (DDRCLKDR) .................................................................... 23-32 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxviii Figures Title Page Number Freescale Semiconductor ...
Page 79
... Trace Buffer Read High Register (TBADHR).................................................................... 25-21 25-16 Trace Buffer Access Data Register (TBADR) .................................................................... 25-22 25-17 Programmed Context ID Register (PCIDR) ....................................................................... 25-22 25-18 Current Context ID Register (CCIDR) ............................................................................... 25-23 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxxix ...
Page 80
... Coherency Module Dispatch (CMD) Trace Buffer Entry .......................................... 25-27 25-21 DDR Trace Buffer Entry ..................................................................................................... 25-28 25-22 PCI Trace Buffer Entry ....................................................................................................... 25-28 25-23 PCI Express Trace Buffer Entry.......................................................................................... 25-29 C-1 MPC8535E Block Diagram ....................................................................................................C-2 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxx Figures Title Page Number Freescale Semiconductor ...
Page 81
... SerDes2 I/O Port Selection ................................................................................................... 4-17 4-18 CPU Boot Configuration....................................................................................................... 4-18 4-19 Boot Sequencer Configuration.............................................................................................. 4-18 4-20 DDR DRAM Type ................................................................................................................ 4-19 4-21 Serdes 2 Reference Clock Configuration.............................................................................. 4-19 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Tables Page Number lxxxi ...
Page 82
... L2CAPTECC Field Descriptions .......................................................................................... 6-21 6-16 L2ERRDET Field Descriptions ............................................................................................ 6-21 6-17 L2ERRDIS Field Descriptions.............................................................................................. 6-22 6-18 L2ERRINTEN Field Descriptions ........................................................................................ 6-23 6-19 L2ERRATTR Field Descriptions .......................................................................................... 6-23 6-20 L2ERRADDRL Field Description........................................................................................ 6-24 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxxii Tables Title Page Number Freescale Semiconductor ...
Page 83
... DDR_SDRAM_MODE_2 Field Descriptions...................................................................... 8-30 8-17 DDR_SDRAM_MD_CNTL Field Descriptions................................................................... 8-31 8-18 Settings of DDR_SDRAM_MD_CNTL Fields .................................................................... 8-32 8-19 DDR_SDRAM_INTERVAL Field Descriptions .................................................................. 8-33 8-20 DDR_DATA_INIT Field Descriptions ................................................................................. 8-33 8-21 DDR_SDRAM_CLK_CNTL Field Descriptions ................................................................. 8-34 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxiii ...
Page 84
... Two Banks with Partial Array Self Refresh Disabled...................................................... 8-68 8-58 Example of Address Multiplexing for 64-Bit Data Bus Interleaving between Four Banks with Partial Array Self Refresh Disabled ....................................... 8-69 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxxiv Tables Title Page Number Freescale Semiconductor ...
Page 85
... CISR0 Field Descriptions ..................................................................................................... 9-31 9-25 CISR1 Field Descriptions ..................................................................................................... 9-32 9-26 CISR2 Field Descriptions ..................................................................................................... 9-32 9-27 PMnMR0 Field Descriptions ................................................................................................ 9-33 9-28 PMnMR1 Field Descriptions ................................................................................................ 9-34 9-29 PMnMR2 Field Descriptions ................................................................................................ 9-34 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxv ...
Page 86
... Fetch FIFO Enqueue Register Field Descriptions .............................................................. 10-44 10-18 Channel Assignment Value ................................................................................................. 10-50 10-19 Field Names in Interrupt Enable, Interrupt Status, and Interrupt Clear Registers .............. 10-51 10-20 IP Block Revision Register Fields ...................................................................................... 10-55 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxxvi Tables Title Page Number Freescale Semiconductor ...
Page 87
... KEU IV_1 Register Fields Description ........................................................................... 10-128 10-59 MDEU Mode Register in Old Configuration.................................................................... 10-133 10-60 MDEU Mode Register in New Configuration .................................................................. 10-134 10-61 Mode Register—HMAC or SSL-MAC Generated by Single Descriptor........................ 10-136 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxvii ...
Page 88
... Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS] .................................. 12-14 12-15 UMCR Field Descriptions .................................................................................................. 12-14 12-16 ULSR Field Descriptions .................................................................................................... 12-15 12-17 UMSR Field Descriptions................................................................................................... 12-16 12-18 USCR Field Descriptions.................................................................................................... 12-17 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxxviii Tables Title Page Number Freescale Semiconductor ...
Page 89
... Boot Bank Field Values after Reset for GPCM as Boot Controller.................................... 13-59 13-35 FCM Chip-Select to First Command Timing...................................................................... 13-68 13-36 FCM Command, Address, and Write Data Timing Parameters.......................................... 13-69 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxix ...
Page 90
... TBPTRn Field Descriptions ................................................................................................ 14-51 14-25 TBASEH Field Descriptions............................................................................................... 14-51 14-26 TBASE0–TBASE7 Field Descriptions ............................................................................... 14-52 14-27 TMR_TXTSn_ID Register Field Descriptions ................................................................... 14-53 14-28 TMR_TXTSn_H/L Register Field Descriptions................................................................. 14-53 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Tables Title Page Number Freescale Semiconductor ...
Page 91
... TRMAX Field Descriptions................................................................................................ 14-90 14-65 TRMGV Field Descriptions................................................................................................ 14-91 14-66 RBYT Field Descriptions.................................................................................................... 14-91 14-67 RPKT Field Descriptions .................................................................................................... 14-92 14-68 RFCS Field Descriptions .................................................................................................... 14-92 14-69 RMCA Field Descriptions .................................................................................................. 14-93 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number xci ...
Page 92
... CAM2 Field Descriptions ................................................................................................. 14-113 14-106 RREJ Field Descriptions ................................................................................................... 14-115 14-107 IGADDRn Field Descriptions........................................................................................... 14-116 14-108 GADDRn Field Descriptions ............................................................................................ 14-116 14-109 FIFOCFG Field Descriptions............................................................................................ 14-117 14-110 ATTR Field Descriptions .................................................................................................. 14-119 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xcii Tables Title Page Number Freescale Semiconductor ...
Page 93
... Signal Encoding for Encoded 8-Bit FIFO......................................................................... 14-159 14-149 Steps for Minimum Register Initialization........................................................................ 14-160 14-150 Custom Preamble Field Descriptions................................................................................ 14-165 14-151 Received Preamble Field Descriptions ............................................................................. 14-166 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number xciii ...
Page 94
... FIFO Interface Mode Signal Configurations ........................................................... 14-232 14-190 8-Bit FIFO Mode Register Initialization Steps ................................................................. 14-233 14-191 SGMII Interface Signal Configuration (4-Wire)............................................................... 14-234 14-192 SGMII Mode Register Initialization Steps........................................................................ 14-234 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xciv Tables Title Page Number Freescale Semiconductor ...
Page 95
... PITARn Field Descriptions ................................................................................................. 16-20 16-12 PIWBAR Field Descriptions............................................................................................... 16-21 16-13 PIWBEAR Field Descriptions ............................................................................................ 16-21 16-14 PIWARn Field Descriptions................................................................................................ 16-22 16-15 ERR_DR Field Descriptions ............................................................................................... 16-24 16-16 ERR_CAP_DR Field Descriptions ..................................................................................... 16-25 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number xcv ...
Page 96
... Power-On Reset Values for Affected Configuration Bits ................................................... 16-68 17-1 POR Parameters for PCI Express Controller ........................................................................ 17-4 17-2 PCI Express Interface Signals—Detailed Signal Descriptions............................................. 17-5 17-3 PCI Express Memory-Mapped Register Map ....................................................................... 17-6 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xcvi Tables Title Page Number Freescale Semiconductor ...
Page 97
... PCI Express Error Capture Register 2 Field Descriptions External Source, Inbound Memory Request Transaction .............................................. 17-41 17-35 PCI Express Error Capture Register 3 Field Descriptions Internal Source, Outbound Transaction.......................................................................... 17-42 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number xcvii ...
Page 98
... PCI Express Interrupt Line Register Field Description ...................................................... 17-66 17-74 PCI Express Interrupt Pin Register Field Description ........................................................ 17-66 17-75 PCI Express Bridge Control Register Field Description .................................................... 17-67 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xcviii Tables Title Page Number Freescale Semiconductor ...
Page 99
... PEX_LTSSM_STAT Status Codes...................................................................................... 17-91 17-112 PEX_GCLK_RATIO Field Descriptions ............................................................................ 17-93 17-113 PEX_PM_TIMER Field Descriptions ................................................................................ 17-94 17-114 PEX_PME_TIMEOUT Field Descriptions ........................................................................ 17-94 17-115 PEX_SSVID_UPDATE Field Descriptions........................................................................ 17-95 17-116 PEX_CFG_READY Field Descriptions ............................................................................. 17-96 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number xcix ...
Page 100
... SNotification Field Descriptions......................................................................................... 19-20 19-17 TransCfg Field Descriptions ............................................................................................... 19-20 19-18 TransStatus Field Descriptions............................................................................................ 19-21 19-19 LinkCfg Field Descriptions................................................................................................. 19-21 19-20 LinkCfg1 Field Descriptions............................................................................................... 19-23 19-21 LinkCfg2 Field Descriptions............................................................................................... 19-23 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Tables Title Page Number Freescale Semiconductor ...
Page 101
... Relationship Between Command CRC Error and Command Timeout Error for Auto CMD12 ............................................................................................................ 20-32 20-22 HOSTCAPBLT Field Descriptions..................................................................................... 20-33 20-23 WML Field Descriptions .................................................................................................... 20-34 20-24 FEVT Field Descriptions .................................................................................................... 20-35 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number ci ...
Page 102
... PRI_CTRL Register Field Descriptions ............................................................................. 21-38 21-34 SI_CTRL Register Field Descriptions ................................................................................ 21-39 21-35 CONTROL Field Descriptions ........................................................................................... 21-40 21-36 Supported PHY Interfaces .................................................................................................. 21-41 21-37 Typ Field Encodings ........................................................................................................... 21-43 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cii Tables Title Page Number Freescale Semiconductor ...
Page 103
... Summary Behavior on Host System Errors ...................................................................... 21-116 21-74 Endpoint Capabilities/Characteristics ............................................................................... 21-118 21-75 Current dTD Pointer.......................................................................................................... 21-119 21-76 Multiple Mode Control ..................................................................................................... 21-120 21-77 Next dTD Pointer .............................................................................................................. 21-120 21-78 dTD Token ........................................................................................................................ 21-121 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number ciii ...
Page 104
... PORDEVSR2 Field Descriptions ....................................................................................... 23-13 23-10 GPPORCR Field Descriptions ............................................................................................ 23-14 23-11 GENCFGR Field Descriptions............................................................................................ 23-14 23-12 PMUXCR Field Descriptions ............................................................................................. 23-15 23-13 DEVDISR Field Descriptions ............................................................................................. 23-17 23-14 PMJCR Field Descriptions.................................................................................................. 23-20 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 civ Tables Title Page Number Freescale Semiconductor ...
Page 105
... Watchpoint and Trigger Signals—Detailed Signal Descriptions .......................................... 25-7 25-5 JTAG Test and Other Signals—Detailed Signal Descriptions .............................................. 25-8 25-6 Debug and Watchpoint Monitor Memory Map..................................................................... 25-9 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number cv ...
Page 106
... PCI Express Controller 1 & 2 Registers ...............................................................................A-11 A-11 GPIO Registers .................................................................................................................... A-15 A-12 SATA Registers .................................................................................................................... A-16 A-13 L2/SRAM Memory-Mapped Registers................................................................................ A-17 0-1 USB Interface Memory Map................................................................................................ A-18 A-2 Module Memory Map .......................................................................................................... A-20 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cvi Tables Title Page Number Freescale Semiconductor ...
Page 107
... C-3 Host/Agent Configuration (MPC8535E) ................................................................................C-4 C-4 SerDes1 I/O Port Selection (MPC8535E)...............................................................................C-4 C-5 SerDes2 I/O Port Selection (MPC8535E)...............................................................................C-5 C-6 Supported SerDes 1 (PCI Express) Configurations ................................................................C-5 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number cvii ...
Page 108
... Table Number MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cviii Tables Title Page Number Freescale Semiconductor ...
Page 109
... MPC8536E. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor provides a high-level description of features and functionality of the describes the memory map of the MPC8536E. An overview of the provides a listing of all the external signals, cross-references for ...
Page 110
... DDR2/DDR3 SDRAM memory describes the security controller of the MPC8536E. The describes the inter-IC (IIC or I describes the (dual) universal asynchronous receiver/transmitters describes the embedded programmable 2 C) bus controllers of the MPC8536E controller to initialize Freescale Semiconductor ...
Page 111
... Chapter 22, “General Purpose I/O (GPIO),” of the MPC8536E. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor describes the enhanced local bus controller (eLBC) describes the two enhanced describes the four-channel general-purpose DMA controller of the describes the PCI interface, which complies with the PCI Local describes the three PCI Express® ...
Page 112
... MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cxii defines the global utilities of the MPC8536E. These include power describes the performance monitor of the History,” contains a list of major differences since the last revision of the describes the debug features and Registers,” lists all Freescale Semiconductor ...
Page 113
... In some contexts, such as signal encodings, an unitalicized x indicates a don’t care italicized x indicates an alphanumeric variable italicized n indicates a numeric variable. ¬ NOT logical operator & AND logical operator | OR logical operator MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor cxiii ...
Page 114
... Term ADB Allowable disconnect boundary ATMU Address translation and mapping unit BD Buffer descriptor BIST Built-in self test MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cxiv Section 3.2, “Configuration Signals Sampled at Reset.” Table i. Acronyms and Abbreviated Terms Meaning Freescale Semiconductor ...
Page 115
... IDL Inter-chip digital link IEEE Institute of Electrical and Electronics Engineers IPG Interpacket gap ITLB Instruction translation lookaside buffer IU Integer unit JTAG Joint Test Action Group LAE Local access error MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Meaning cxv ...
Page 116
... Real-time operating system RWITM Read with intent to modify RMW Read modify write Rx Receive RxBD Receive buffer descriptor SCC Serial communication controller SCP Serial control port SDLC Synchronous data link control MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cxvi Meaning Freescale Semiconductor ...
Page 117
... TSA Time-slot assigner TSEC Three-speed Ethernet controller Tx Transmit TxBD Transmit buffer descriptor UART Universal asynchronous receiver/transmitter UPM User-programmable machine UTP Unshielded twisted pair VA Virtual address ZBT Zero bus turnaround MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Meaning cxvii ...
Page 118
... MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cxviii Freescale Semiconductor ...
Page 119
... MPC8536E. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor provides a high-level description of features and functionality of the describes the memory map of the MPC8536E. An overview of the provides a listing of all the external signals, cross-references for ...
Page 120
... MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 I-2 Freescale Semiconductor ...
Page 121
... The MPC8536E is also available without a security engine configuration known as the MPC8536. All specifications other than those relating to security apply to the MPC8536 exactly as described in this document. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor 2 C controllers, a four-channel DMA controller, an enhanced 1 ...
Page 122
... SATA w/ IEEE 1588 SGMII 2 Lane SERDES Figure 1-1. MPC8536E Block Diagram shows the major functional units Power Management 64-bit Async DDR2/DDR3 eSPI Queue SDRAMController DUART 2 with ECC PCI 32 Gigabit Ethernet w/ IEEE 1588 PCI-e PCI-e SGMII PCI-e 8 Lane SERDES Freescale Semiconductor DMA ...
Page 123
... L2 cache in order to maintain coherency across local cacheable memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be routed or dispatched to target modules on the device. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Overview 3 ...
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... Random number generator (RNGB) 1.3.4 High-Speed Interface Blocks (SerDes) The MPC8536E offers two high-speed SerDes interface blocks. These blocks are connected to the SGMII, PCI Express, and SATA interfaces as described in this section. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Freescale Semiconductor ...
Page 125
... Table 1-2. Supported eTSEC1 and eTSEC3 Configurations Mode Option Ethernet standard interfaces Ethernet reduced interfaces FIFO interface MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Section 4.4.3.8, “SerDes1 I/O Port PCI Express Signal/Lane 2/C 3/D 4/E 1 ...
Page 126
... Support external PHY with UTMI+ low-pin interface (ULPI) 1.3.6.2 Device Mode Operation • Support operation as a stand-alone USB device — Support one upstream facing port — Support six programmable USB endpoints MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Freescale Semiconductor ...
Page 127
... Support for dynamic and static power management to minimize power consumption of idle blocks: — Doze, nap, and sleep modes for dynamic power management — Deep sleep mode for static power management MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Overview 7 ...
Page 128
... The eSPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (receive, transmit, clock, and slave select). The eSPI block consists of transmitter and receiver sections, an independent baud-rate generator, and a control unit. It has the ability to boot from an SPI serial flash device. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Freescale Semiconductor ...
Page 129
... To chain (both extended and direct) through local memory-mapped chain descriptors. • To handle misaligned transfers, as well as stride transfers and complex transaction chaining. • To specify local attributes such as snoop and L2 write stashing. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor 2 C, DUART, eLBC Overview 9 ...
Page 130
... Three protocol engines on a per-chip-select basis • Parity support • Default boot ROM chip select with configurable bus width (8, 16 bits) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Freescale Semiconductor ...
Page 131
... PWR_EN 802.11 USB Hub User Port User Port UPLI ULPI PHY PHY Figure 1-2. Multi-Function Printer Application MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor DDR-2/DDR-3 NAND SDRAM Flash SODIMM VDD2 Local Bus X64 MPC8536E USB Host SEC USB Device ...
Page 132
... Figure 1-3. Network Attached Storage Application MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev DDR-2/DDR-3 NAND SDRAM Flash Memory 1G SODIMM Local Bus X64 + ECC 100/1000 Ethernet MPC8536E 100/1000 Ethernet XOR Accelerator USB Device SATA NV SPI GBE PHY LAN GBE PHY LAN Freescale Semiconductor ...
Page 133
... MPC8536E GHz performance in low power envelopes provides the mechanism for the designer to create high performance in a fanless system. Expansion ULPI Port PHY Maintenance ULPI Port PHY MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor DDR-2/DDR-3 NAND SDRAM Flash SODIMM Local Bus X64 USB Host MPC8536E 100/1000 ...
Page 134
... MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev DDR-2/DDR-3 NAND SDRAM Flash SODIMM Local Bus X64 + ECC USB Host MPC8536E USB Device 100/1000 Ethernet 100/1000 Ethernet PCIe x4 ASIC/FPGA Figure 1-5. Network Controller Application NV Memory SPI 5/9 Port SGMII GE Switch w/PHY Freescale Semiconductor ...
Page 135
... Table 2-1. PCI PCI Express 2 PCI Express 1 PCI Express 3 Enhanced local bus Configuration space DDR SDRAM MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 2-1. Target Interface Codes Source/Target Interface Target Code 00000 00001 00010 00011 00100 01000 ...
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... Size 0x0_0000_0000 2 Gbytes 0b1111 (DDR SDRAM) 0x0_8000_0000 1 Mbyte 0b0100 (Enhanced local bus) 0x0_A000_0000 256 Mbytes 0b0000 (PCI) 0x0_C000_0000 256 Mbytes 0b0100 (Enhanced local bus) 0x8_0000_0000 32 Gbytes 0b0100 (PCI Express) Unused 0x0_A000_0000 PCI 0x0_B000_0000 0x0_C000_0000 Enhanced Local Bus Target Interface Freescale Semiconductor ...
Page 137
... High-order address bits defining location of the window in the initial address space Window size/attributes Window enable, window size, target interface, and transaction attributes MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Location”). However, note that the e500 core Table 2-3 summarizes the general ...
Page 138
... The local access window registers exist as part of the local access block in the general utilities registers. See Section 2.3.4, “General Utilities Registers.” MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-4 Section 2.1, “Local Memory Map Overview and A detailed description of the local access window for Freescale Semiconductor ...
Page 139
... LAWBAR8—Local access window 8 base address register 0x0_0D10 LAWAR8—Local access window 8 attribute register 0x0_0D28 LAWBAR9—Local access window 9 base address register 0x0_0D30 LAWAR9—Local access window 9 attribute register MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Register Memory Map Access Reset Section/Page R 0x0000_0000 2 ...
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... IP_INT All zeros Table 2-6. LAIPBRR2 Field Descriptions Description Access Reset Section/Page R/W 0x0000_0000 2.2.3.5/2-7 R/W 0x0000_0000 2.2.3.5/2-7 R/W 0x0000_0000 2.2.3.5/2-7 R/W 0x0000_0000 2.2.3.5/2-7 2-2. Access: Read only 23 24 IP_MJ IP_MN 2-3. Access: Read only 23 24 IP_CFG Freescale Semiconductor 31 31 ...
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... LAWSR11: 0x0_0D70 — W Reset Figure 2-5. Local Access Window n Attributes Registers (LAWAR0–LAWAR7) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Description 8 BASE_ADDR All zeros Table 2-7. LAWBAR n Field Descriptions Description 11 12 TRGT_ID All zeros Access: Read/Write Access: Read/Write 25 26 — ...
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... MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-8 Table 2-8. LAWAR n Field Descriptions Description bytes Table 2-9, local access window 1 governs the mapping of the 1-Mbyte Size 1 Mbyte 0b0100 (Local bus controller —LBC) 2 Gbytes 0b1111 (DDR SDRAM) (SIZE+1) bytes. Target Interface Freescale Semiconductor ...
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... The PCI Express interface has four outbound ATMU windows plus a default window. The PCI Express outbound ATMU registers include an extended translation address register so that bits of external MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Memory Map for a detailed description of the ...
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... MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-10 Section 17.3.5.1, “PCI Express Outbound ATMU Registers” Section 16.3.1.3, “PCI ATMU Inbound for a description of the PCI Express inbound ATMU windows. NOTE for a Section 17.3.5.1, “PCI Section 4.3.1.1.2, The default value for Freescale Semiconductor ...
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... Table 2-10. Local Memory Configuration, Control, and Status Register Summary Offset from CCSRBAR 0x0_0000–0x3_FFFF 0x4_0000–0x7_FFFF 0x8_0000–0xB_FFFF 0xC_0000–0xD_FFFF 0xE_0000–0xF_FFFF MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Register Grouping General utilities Programmable interrupt controller (PIC) Reserved Reserved Device-specific utilities Memory Map Section 16.3.2.11, “ ...
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... B000 USB3 0x2 C000 0x2 E000 eSDHC 0x2 F000 0x3 0000 SEC 0x3 FFFF and Status Memory Block General Utility Block 0xn n000 General Registers 0xn nC00 ATMU 0xn nE00 Error Mgmt 0xn nF00 Debug Freescale Semiconductor ...
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... Also, when reading from a register, software should not rely on the value of any reserved bit remaining consistent. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor NOTE PIC Registers 0x4 0000 ...
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... Special is used when no other category applies. In this case the register figure and field description table should be read carefully. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-14 0xE 0000 0xE 1000 0xE 2000 0xF FFFC and Status Memory Block Device-Specific Registers Global Utilities Perf. Monitor Watchpoint/Debug Freescale Semiconductor ...
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... DMA controller 0x2_2000 USB controller 1 0x2_3000 USB controller 2 0x2_4000 eTSEC1 0x2_5000 Reserved MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 2-11. CCSR Block Base Address Map Block Section/Page General Utilities (0x0_0000–0x3_FFFF) 16.3/16-11 19.3.1/19-4 19.3.1/19-4 14.5/14-14 Comments 4.3.1/4-4 ...
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... Device Specific Utilities (0xE_0000–0xF_FFFF) 23.4/23-3 24.3/24-3 25.3/25-9 23.4/23-3 23.4/23-3 1 Comments — — — USB1 is at 0x2_2000; USB2 is at 0x2_3000; — — — — — — — — — — — — — — — — — — — — Freescale Semiconductor ...
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... PCI Express 1, 2, and 3 interface signals • SATA and SGMII signals • System control, power management, and debug signals • Test, JTAG, configuration, and clock signals • USB interface signals • eSDHC signals MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor NOTE 3-1 ...
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... DDR memory — PCI — No. of Table/ I/O Signals Page 64 I/O 8-3/8-6 8 I/O 8-3/8 8-3/8 8-3/8-6 8 I/O 8-3/8-6 1 I/O 8-3/8-6 8 I/O 8-3/8-6 1 I/O 8-3/8 8-3/8 8-3/8 8-3/8 8-3/8 8-3/8 8-3/8 8-3/8 8-3/8 8-3/8-6 2 I/O 8-3/8 8-3/8 8-3/8-6 32 I/O 16-2/16-6 Freescale Semiconductor ...
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... TSEC1_TX_EN TSEC1 transmit enable TSEC1_TX_ER TSEC1 transmit error TSEC1_TX_CLK TSEC1 transmit clock in TSEC1_GTX_CLK TSEC1 transmit clock out TSEC1_CRS TSEC1 carrier sense MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block PCI — PCI — PCI — ...
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... No. of Table/ I/O Signals Page 1 I 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14-10 1 I/O 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14-10 32 I/O 13-2/13-5 4 I/O 13-2/13-5 Freescale Semiconductor ...
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... DMA_DDONE[0:1] DMA done 0–1 DMA_DDONE2 DMA done 2 DMA_DDONE3 DMA done 3 MCP Machine check processor UDE Unconditional debug event IRQ[0:8] External interrupt 0–8 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block eLBC cfg_cpu_boot eLBC cfg_sys_pll[0:3] eLBC — eLBC DMA_DREQ2 ...
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... System control — System control — No. of Table/ I/O Signals Page 1 I 9-3/9 9-3/9 9-3/9 9-3/9 12-1/12 12-1/12 12-1/12 12-1/12-3 1 I/O 11-2/11-4 1 I/O 11-2/11-4 1 I/O 11-2/11-4 1 I/O 11-2/11 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17 4-2/4 4-2/4 4-2/4 23-2/23-2 Freescale Semiconductor ...
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... USB1_PWRFAULT USB1 power fault USB1_PCTL0 USB1 port control 0 USB1_PCTL1 USB1 port control 1 USB1_CLK USB1 clock USB2_D[7:0] USB2 data MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block System control — System control TRIG_OUT Power mgmt — ...
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... I/O 20-1/20 20-1/20-4 1 I/O 20-1/20-4 4 I/O 20-1/20 20-1/20 20-1/20-4 1 I/O 18-1/18 18-1/18 18-1/18-4 4 I/O 18-1/18-4 2 I/O 22-1/22-2 1 I/O 22-1/22-2 1 I/O 22-1/22-2 1 I/O 22-1/22-2 1 I/O 22-1/22-2 1 I/O 22-1/22-2 1 I/O 22-1/22-2 1 I/O 22-1/22-2 1 I/O 22-1/22-2 2 I/O 22-1/22-2 2 I/O 22-1/22-2 2 I/O 22-1/22-2 Freescale Semiconductor ...
Page 159
... Hard reset request 2 IIC1_SCL I C serial clock 2 IIC1_SDA I C serial data 2 IIC2_SCL I C serial clock MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block Power mgmt — System control — System control — Clock — DMA GPIO[10:11] ...
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... I/O Signals Page 1 I/O 11-2/11 9-3/9 9-3/9 9-3/9 9-3/9 9-3/9 25-5/25 25-5/25 13-2/13 13-2/13-5 32 I/O 13-2/13 13-2/13 13-2/13 13-2/13 13-2/13-5 1 I/O 13-2/13 13-2/13 13-2/13-5 4 I/O 13-2/13 13-2/13 13-2/13 13-2/13 13-2/13-5 1 I/O 13-2/13 13-2/13 25-5/25 13-2/13 13-2/13 13-2/13 13-2/13 8-3/8-6 Freescale Semiconductor ...
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... PCI_DEVSEL PCI device select PCI_FRAME PCI frame PCI_GNT[3:4] PCI grant 3 PCI_GNT0 PCI grant 0 PCI_GNT1 PCI grant 1 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block DDR memory — DDR memory — DDR memory — DDR memory — ...
Page 162
... SATA, SGMII — eSDHC GPIO4 No. of Table/ I/O Signals Page 1 O 16-2/16 16-2/16-6 1 I/O 16-2/16-6 1 I/O 16-2/16-6 1 I/O 16-2/16 16-2/16 16-2/16-6 1 I/O 16-2/16-6 1 I/O 16-2/16-6 1 I/O 16-2/16-6 1 I/O 16-2/16 23-2/23 23-2/23 4-2/4 4-3/4 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17 20-1/20-4 Freescale Semiconductor ...
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... TSEC1 collision detect TSEC1_CRS TSEC1 carrier sense TSEC1_GTX_CLK TSEC1 transmit clock out TSEC1_RX_CLK TSEC1 receive clock TSEC1_RX_DV TSEC1 receive data valid MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block eSDHC — eSDHC — eSDHC — ...
Page 164
... Dual UART — No. of Table/ I/O Signals Page 1 I 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14-10 1 I/O 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 14-2/14- 12-1/12 12-1/12 12-1/12 12-1/12-3 Freescale Semiconductor ...
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... Most of the reset configuration signals have internal pull-up resistors so that if the signals are not driven, the default value is high (a one), as shown in the table. Some signals do not have MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) ...
Page 166
... EC_MDC TSEC1_TXD[7:4] TSEC1_TXD3 TSEC1_TXD2 TSEC1_TXD[1:0] cfg_tsec1_prtcl[1:0] TSEC1_TX_ER TSEC3_TXD7 TSEC3_TXD[6:4] TSEC3_TXD3 cfg_srds2_ref_clk0 TSEC3_TXD2 TSEC3_TXD[1:0] cfg_tsec3_prtcl[1:0] TSEC3_TX_ER TSEC_1588_TRIG_OUT[0:1] TSEC_1588_CLK_OUT TSEC_1588_PULSE_OUT1 TSEC_1588_PULSE_OUT2 cfg_srds2_ref_clk1 Default Name cfg_pci_impd 1 cfg_pci_arb 1 cfg_eng_use0 1 cfg_rom_loc[0:3] 1111 cfg_eng_use1 1 cfg_srds2_prtcl0 11 cfg_tsec1_reduce cfg_eng_use2 1 cfg_io_ports[0:2] 111 cfg_srds2_prtcl1 1 11 cfg_tsec3_reduce 1 cfg_ddr_pll[0:1] cfg_ddr_pll2 cfg_srds2_prtcl2 Freescale Semiconductor ...
Page 167
... Table 3-4. Output Signal States During System Reset Interface DDR Memory DDR Memory DDR Memory DDR Memory DDR Memory MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Reset Configuration Functional Signal Name LAD[0:31] LA27 LA[28:31] LWE0/LBS0/LFWE LWE[1:3]/LBS[1:3] LBCTL ...
Page 168
... TRIG_OUT/READY/ QUIESCE Input—reset config (test only) TDO ASLEEP Input—reset config (test only) State During Reset Driven High Driven Low High-Z High-Z Driven Low High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Driven Low High-Z High-Z High-Z Freescale Semiconductor ...
Page 169
... Table 3-4. Output Signal States During System Reset (continued) Interface Power management System Control System Control MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Signal State During Reset POWER_EN Driven High CKSTP_OUT High-Z HRESET_REQ Input—reset config (test only) ...
Page 170
... Signal Descriptions MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 3-20 Freescale Semiconductor ...
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... Second SERDES high-speed interface reference clock SD2_REF_CLK The following sections describe the reset and clock signals in detail. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor contains references to additional sections that contain more information. Table 4-1. Signal Summary Description Table 4-2 ...
Page 172
... TOSR[SEL] equals 0b000. See Section 4.4.2, “Power-On Reset Sequence,” Subsequent assertion/negation due to power down modes occurs asynchronously. Section 4.4.3, “Power-On Reset and Section 4.4.3, “Power-On Section 11.4.5, “Boot Chapter 25, “Debug Features and Watchpoint for more information. Freescale Semiconductor ...
Page 173
... It also contains a brief description of the boot sequencer which may be used to initialize configuration registers or memory before the CPU is released to boot. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Reset, Clocking, and Initialization Section 4.4.4, “Clocking,” they are defined Description Section 4.4.3.3, “ ...
Page 174
... Read the current value of CCSRBAR using a load word instruction followed by an isync. This forces all accesses to configuration space to complete. – Write the new value to CCSRBAR. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-4 Register Access Reset Section/Page R/W 0x000F_F700 4.3.1.1.2/4-5 R/W 0x0000_0000 4.3.1.2.1/4-6 R/W 0x0000_0000 4.3.1.2.1/4-6 R/W 0x0000_0000 4.3.1.3.1/4-7 Freescale Semiconductor ...
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... This prevents problems with incorrect mappings if subsequent configuration of the local access windows uses a different target mapping for the address specified in ALTCBAR. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor 7 8 BASE_ADDR 1 Table 4-5 ...
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... Second configuration window is enabled. 1–6 — Write reserved, read = 0 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev BASE_ADDR All zeros Table 4-6. ALTCBAR Bit Settings Description TRGT_ID All zeros Table 4-7. ALTCAR Bit Settings Description Access: Read/Write — Access: Read/Write 31 — Freescale Semiconductor ...
Page 177
... EN — W Reset Figure 4-4. Boot Page Translation Register (BPTR) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 4-7. ALTCAR Bit Settings (continued) Description 00101–01011 Reserved 01000 Configuration, control, status registers 01001–01110 Reserved 01111 Local memory—DDR SDRAM and on-chip SRAM Section 4.4.3.6, “ ...
Page 178
... Description Section 4.4.3.11, “Boot Sequencer Configuration.” Section 11.4.5, “Boot Sequencer Mode,” for more information on the setting of the soft reset flag. Note 2 C interface and writes data to The boot sequencer the I C chapter. Section 23.4.1.16, “Machine Section 4.4.2, Freescale Semiconductor ...
Page 179
... ROMs on the I2C1 interface, as described in Section 11.4.5, “Boot Sequencer MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Mode,” and Section 11.4.5.2, “EEPROM Data Section 23.4.1.22, “Reset Control Register NOTE: Section 4.4.3.6, “ ...
Page 180
... Section 4.4.3.10, “CPU Boot Configuration.” Section 25.3.4.1, “Trigger Out Source Register (TOSR),” Section 25.3.4, “Trigger Out Function.” Section 23.4.1, “Register Descriptions.” Figure 4-5. Power-On Reset Sequence The MPC8536E for more For more Section 4.5.1, “System Boot.” Freescale Semiconductor ...
Page 181
... PORPLLSR (POR PLL status register), as described in Status Register (PORPLLSR).” Note that x8 PCI Express is only available at CCB clock rates of 527 MHz and above. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor NOTE Table 4-9, establish the clock ratio between the SYSCLK input and the ...
Page 182
... Table 4-10. e500 Core Clock PLL Ratios Reset Configuration Name Value (Binary) cfg_core_pll[0:2] CCB Clock : SYSCLK Ratio Reserved Reserved Reserved Reserved Reserved Reserved Reserved (default) Section 5.3, “Summary of Core e500 Core: CCB ClockRatio 000 001 (4.5:1) 010 Reserved 011 (1 100 101 (2.5:1) 110 111 (3 (default) Freescale Semiconductor ...
Page 183
... Functional Reset Configuration Signal Name LGPL1/LFALE cfg_sys_speed Default (1) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 4-11, establish the clock ratio between the DDRCLK input and the Table 4-11. DDR Complex Clock PLL Ratios cfg_ddr_pll[0:2] 000 001 010 ...
Page 184
... MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-14 Table 4-13 configure internal logic for proper operation Table 4-13. Core Speed Configuration Value Name (Binary) 0 Core frequency at or below 800 MHz 1 Core frequency above 800 MHz Table 4-14, select the physical location of boot ROM. Accesses Meaning Freescale Semiconductor ...
Page 185
... Note that the values latched on these signals during POR are accessible through the memory-mapped PORBMSR (POR boot mode status register) described in Register (PORBMSR).” MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 4-14. Boot ROM Location Value (Binary) ...
Page 186
... PCI Express 1 (x4) (2.5 Gbps) PCI Express 2 (x2) (2.5 Gbps) PCI Express 3 (x2) (2.5 Gbps) Meaning . Table 4-16 shows the SerDes1 Meaning SerDes1 Lanes A–D 1 SerDes1 Lanes A–H SerDes1 Lanes A–D SerDes1 Lanes E–H SerDes1 Lanes A–D SerDes1 Lanes E–F SerDes1 Lanes G–H Freescale Semiconductor ...
Page 187
... The external master frees the CPU to boot by setting EEBPCR[CPU_EN] in the ECM CCB port configuration register (EEBPCR). See Register (EEBPCR),” for more information. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor on SerDes2 NOTE Blocks.” Table 4-17. SerDes2 I/O Port Selection ...
Page 188
... C addressing mode is used. Boot sequencer is enabled and loads configuration information from a ROM on the I ROM must be present. 11 Boot sequencer is disabled NOTE Section 4.4.3.10, “CPU Boot Meaning Section 11.4.5, Meaning 2 C interface. A valid 2 C1 interface. A valid 2 C ROM is accessed (default). Configuration.” Freescale Semiconductor ...
Page 189
... Table 4-21. Serdes 2 Reference Clock Configuration Functional Reset Configuration Signal Name TSEC3_TXD3, cfg_srds2_ref_clk[0:1] TSEC_1588_ PULSE_OUT2 Default (11) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 4-20 describes the configuration of the DDR Table 4-20. DDR DRAM Type Value (Binary) 0 DDR3 1.5 V, CKE low at reset 1 DDR2 1.8 V, CKE low at reset (default) Section 23.4.1.6, “ ...
Page 190
... Table 4-23. eTSEC3 Width Configuration Value (Binary) 0 eTSEC3 Ethernet interface operates in reduced mode, either RTBI, RGMII or RMII. 1 eTSEC3 Ethernet interface operates in standard TBI, GMII, MII, or 8-bit FIFO mode (default). Section 23.4.1.4, “POR Meaning Section 23.4.1.4, “POR Meaning Freescale Semiconductor ...
Page 191
... Reset Configuration Functional Signal Name TSEC3_TXD[0:1] cfg_tsec3_prtcl[0:1] Default (11) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 4-24, select the protocol (FIFO, MII, GMII or TBI) used by Table 4-24. eTSEC1 Protocol Configuration Value (Binary) 00 The eTSEC1 controller operates using 8-bit FIFO protocol. ...
Page 192
... Table 4-28. PCI I/O Impedance Value (Binary) 0 25- I/O drivers are used on the PCI interface. 1 42- I/O drivers are used on the PCI interface (default). Clock” for more Section 23.4.1.4, “POR Device Meaning Meaning select the impedance of the PCI I/O Meaning Freescale Semiconductor ...
Page 193
... Note that the value latched on this signal during POR is accessible through the memory-mapped PORDBGMSR (POR debug mode register) described in Register (PORDBGMSR).” MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 4-29, enable the on-chip PCI arbiter. Note that the Table 4-29. PCI Arbiter Configuration ...
Page 194
... Table 4-32, configure the value of the general-purpose POR Section 23.4.1.7, “General-Purpose POR Configuration Register Value (Binary) — General-purpose POR configuration vector to be placed in GPPORCR (PORDEVSR2).” Value (Binary) 000–110 Reserved 111 Default operation Meaning Meaning Figure 4-6, the Freescale Semiconductor ...
Page 195
... Clocks for these high speed interfaces on the MPC8536E are derived from a PLL in the SerDes block. This PLL is driven by a reference clock (SDn_REF_CLK/SDn_REF_CLK) whose input frequency is a function of the protocol and bit rate being used as shown in Interfaces PCI Express SGMII MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor e500 Core core_clk Core PLL CCB_clk ...
Page 196
... RTC signal to clock the global timers in the PIC unit. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-26 Selection,” describes various high-speed interface configuration PCI Express link width 8 (TCRA–TCRB),” provides additional information on the use of Section 4.4.3.1, Freescale Semiconductor ...
Page 197
... ROM in boot ROM location (see ROM. The on-chip ROM is selected by configuring the POR config pins cfg_rom_loc[0:3]. Prior to boot, the user must ensure that the SD/MMC card to boot from is inserted. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor HID0 TBEN TBL ...
Page 198
... Initial setting will use a serial clock below 400 kHz; the SD/MMC internal registers are read by initialization code and parsed to determine the optimal clock frequency supported by the SD/MMC card inserted. • High speed cards are supported (up to 50MHz SD and 52MHz MMC). MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-28 Freescale Semiconductor ...
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... BOOT signature, it means that the SD/MMC card doesn't contain a valid user code. In such case the boot loader code will disable the eSDHC and will issue a hardware reset request of the SoC by setting RSTCR[HRESET_REQ]. 0x44–0x47 Reserved MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor 0x00 Reserved 0x3F 0x40 Control Words ...
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... User’s code. Note that user's code must start on a 512-byte boundary <=40 if compatibility with FAT12/FAT16/FAT32 filesystems is required. Refer to FAT12/FAT16/FAT32 Filesystems” for details. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-30 Data Bits [0:31] ... Section , “Notes on compatibility with Freescale Semiconductor ...