MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 477

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

it to whichever internal location is indicated by the address. For a read, the controller goes to the internal
location, fetches the requested data from the specified address (if allowed), and returns it over the system
bus.
Host-controlled access is much more CPU-intensive than channel-controlled access, and requires a great
deal of familiarity with the EU and controller registers and procedures. If host-controlled access is used, it
is recommended that only a single EU be operated at a time. Snooping is not available through this
interface.
10.5.1.2
Channel-controlled access is the SEC’s normal operating mode. The controller performs data transfers
based on information from the channels’ descriptors. The controller can queue up to four requests. The
controller dequeues requests and performs the required transfer. Most transfers involve not only the
internal bus, but also the SoC’s master bus with the controller as bus master.
When the SEC performs a read or write transaction as master, in some cases the intended target (for
instance, system memory) may terminate the transaction due to an error. Once the transaction is posted to
the SoC’s target queue, it is the SoC’s responsibility to either complete the transaction or signal an error.
An error in an SEC-initiated transaction is also reported by the SEC through the channel interrupt status
register (ISR). The host is able to determine which channel generated the interrupt by checking the ISR for
the channel ERROR bit.
10.5.1.2.1
A detailed description for a system bus read with controller as master is as follows:
Freescale Semiconductor
1. Channel asserts bus read request to the controller
2. Channel furnishes external read address, internal write address, and transfer length
3. Controller asserts request to the system bus through the master interface
4. Controller waits for system bus read to begin
5. When bus read begins, controller receives data from the master interface and performs a write to
6. Transfer continues until the bus read is completed and the controller has written all data to the
the appropriate internal address supplied by the channel. Data may be realigned byte-wise by the
controller if either:
— the external read address was not on an 8-byte boundary, or
— the internal write address was not on an 8-byte boundary.
appropriate internal address. The master interface continues making bus requests until the full data
length has been read.
Channel-Controlled Access
Host-controlled access of execution units is provided primarily for system
debug purposes. The SEC contains no mechanism to arbitrate between host
and channel accesses to EUs. Simultaneous use of an execution unit by a
channel and a host is liable to force the execution unit into an error
condition.
Channel Controlled Read—Detailed Description
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
Security Engine (SEC) 3.0
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