MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1638

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Complete List of Configuration, Control, and Status Registers
A-26
0x2_46CC RUND—Receive undersize packet counter
0x2_46DC RDRP—Receive drop counter
0x2_46AC RBCA—Receive broadcast packet counter
0x2_46BC RALN—Receive alignment error counter
0x2_46C0 RFLR—Receive frame length error counter
0x2_46C4 RCDE—Receive code error counter
0x2_46C8 RCSE—Receive carrier sense error counter
0x2_46D0 ROVR—Receive oversize packet counter
0x2_46D4 RFRG—Receive fragments counter
0x2_46D8 RJBR—Receive jabber counter
0x2_46EC TBCA—Transmit broadcast packet counter
0x2_46FC TSCL—Transmit single collision packet counter
0x2_470C TNCL—Transmit total collision counter
0x2_471C TFCS—Transmit FCS error counter
0x2_472C TFRG—Transmit fragments frame counter
0x2_46B0 RXCF—Receive control frame packet counter
0x2_46B4 RXPF—Receive PAUSE frame packet counter
0x2_46B8 RXUO—Receive unknown OP code counter
0x2_46E0 TBYT—Transmit byte counter
0x2_46E4 TPKT—Transmit packet counter
0x2_46E8 TMCA—Transmit multicast packet counter
0x2_46F0 TXPF—Transmit PAUSE control frame counter
0x2_46F4 TDFR—Transmit deferral packet counter
0x2_46F8 TEDF—Transmit excessive deferral packet counter
0x2_4700 TMCL—Transmit multiple collision packet counter
0x2_4704 TLCL—Transmit late collision packet counter
0x2_4708 TXCL—Transmit excessive collision packet counter
0x2_4710 Reserved
0x2_4714 TDRP—Transmit drop frame counter
0x2_4718 TJBR—Transmit jabber frame counter
0x2_4720 TXCF—Transmit control frame counter
0x2_4724 TOVR—Transmit oversize frame counter
0x2_4728 TUND—Transmit undersize frame counter
eTSEC1
Offset
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table A-2. Module Memory Map (continued)
Name
1
eTSEC Transmit Counters
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
2
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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