MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1623

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A.1.10
Freescale Semiconductor
0xE28–
0xF00–
0x018–
0xEFC
Offset
0xE0C
0xE1C
0xFFC
Offset
0x00C
0x01C
0xE00
0xE04
0xE08
0xE10
0xE14
0xE18
0xE20
0x000
0x004
0x008
0x010
0x014
0x020
PCI Express Controllers
ERR_DR—PCI error detect register
ERR_CAP_DR—PCI error capture disabled register
ERR_EN—PCI error enable register
ERR_ATTRIB—PCI error attributes capture register
ERR_ADDR—PCI error address capture register
ERR_EXT_ADDR—PCI error extended address capture
register
ERR_DL—PCI error data low capture register
ERR_DH—PCI error data high capture register
GAS_TIMR—PCI gasket timer register
Reserved
Reserved for debug
PEX_CONFIG_ADDR—PCI Express configuration address
register
PEX_CONFIG_DATA—PCI Express configuration data
register
Reserved
PEX_OTB_CPL_TOR—PCI Express outbound completion
timeout register
PEX_CONF_RTY_TOR—PCI Express configuration retry
timeout register
PEX_CONFIG—PCI Express configuration register
Reserved
PEX_PME_MES_DR—PCI Express PME & message detect
register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Express Controller 1—Block Base Address 0x0_A000
PCI Express Controller 3—Block Base Address 0x0_B000
PCI Express Controller 2—Block Base Address 0x0_9000
PCI Express Power Management Event & Message Registers
Table A-10. PCI Express Controller 1 & 2 Registers
Table A-9. PCI Controller Registers (continued)
PCI Controller—Block Base Address 0x0_8000
PCI Express Configuration Access Registers
Register
Register
PCI Error Management Registers
Complete List of Configuration, Control, and Status Registers
Access
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
w1c
—
—
—
—
0x0010_FFFF
0x0400_FFFF
0x0100_3FFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Reset
—
—
—
—
16.3.1.4.1/16-24
16.3.1.4.2/16-25
16.3.1.4.3/16-26
16.3.1.4.4/16-27
16.3.1.4.5/16-28
16.3.1.4.6/16-28
16.3.1.4.7/16-29
16.3.1.4.8/16-29
16.3.1.4.9/16-29
17.3.2.1/17-10
17.3.2.2/17-10
17.3.2.3/17-11
17.3.2.4/17-12
17.3.2.5/17-12
17.3.3.1/17-13
Section/Page
Section/Page
A-11