MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 432

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
In addition to the execution units, SEC 3.0 also includes:
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— Implements CRC32C as required for iSCSI header and payload checksums, CRC32 as required
— ICV checking
DEU—Data Encryption Standard execution unit
— DES, 3DES
— Two key (K1, K2, K1) or Three Key (K1, K2, K3)
— ECB, CBC, CFB-64 and OFB-64 modes for both DES and 3DES
KEU—Kasumi execution unit
— Implements cipher and authentication modes f8 and f9 used in 3G, A5/3 for GSM and EDGE,
— 128-bit confidentiality key and 128-bit integrity key
— ICV checking for f9
MDEU—Message digest execution unit
— Implements SHA with 160-, 224-, 256-, 384-, or 512-bit message digest (as specified by the
— Implements MD5 with 128-bit message digest (as specified by RFC 1321)
— Implements HMAC computation with either message digest algorithm (as specified in RFC
— Implements SSL MAC computation
— ICV checking
PKEU—Public key execution unit that supports the following:
— RSA and Diffie-Hellman
— Elliptic curve cryptography
— Run time equalization to protect against timing and power attacks
RNGU—Random number generator unit
— True Random Number Generator (TRNG)
A context switching polychannel, permitting operation of up to four virtual channels, where each
channel:
— Supports a queue of commands (descriptor pointers) to be executed
— Provides dynamic arbitration for needed crypto-execution units
— Manages up to two execution units (one ciphering and one hashing), and configures for any
— Performs flow-control management of buffer FIFOs on the inputs and outputs of execution
for IEEE 802 packets, as well as for programmable CRC polynomials
and GEA3 for GPRS
FIPS 180-2 standard)
2104 and FIPS-198)
– Programmable field size up to 4096 bits
– F
– Programmable field size up to 1023 bits
required data transfers from one to another
units
2
m and F
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
p
modes
Freescale Semiconductor