MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1259
MPC8536DS
Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(1706 pages)
3.MPC8536DS.pdf
(2 pages)
4.MPC8536DS.pdf
(126 pages)
Specifications of MPC8536DS
Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 19-26
19.3.6
Each entry in the command header table consists of the structure shown in
Freescale Semiconductor
10–28
0–15
Bits
16
17
18
19
29
Command Header
describes the SYSPR fields.
PRI_DATA
RD_SAFE
PRI_DES
In this chapter, “word” refers to 4 bytes or 32 bits.
Name
—
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Data high priority enable.
0 Normal operation. SATA data transfers have default (low) priority.
1 High priority enabled for SATA data transfers.
Reserved
Descriptor fetch high priority enable.
0 Normal operation. SATA descriptor fetches have default (low) priority.
1 High priority enabled for SATA descriptor fetches.
Reserved
Reserved
Read safe. This bit should be set only if the target of the read DMA operation is a well
behaved memory that is not affected by the read operation and which will return the same
data if read again from the same location. This means that unaligned reading operation can
be rounded up to enable more efficient read operations.
0 It is not safe to read more bytes that were intended.
1 It is safe to read more bytes that were intended.
31
R
R
R
Table 19-26. SYSPR Field Descriptions
Command Descriptor Address (CDA)
Command Descriptor Address (CDA)
Command Descriptor Address (CDA)
Reserved
Reserved
Reserved
Figure 19-27. Command Header
Total Transfer Length (TTL)
Total Transfer Length (TTL)
Total Transfer Length (TTL)
PRD_ENTRY
PRD_ENTRY
PRD_ENTRY
23
NOTE
V
V C Q R B A
V C Q R B A
•
•
•
15
C
R
R
R
Q R B A
Description
FIS_LEN
FIS_LEN
FIS_LEN
7
TAG
TAG
TAG
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0
Figure
Word 0
Word 1
Word 2
Word 3
•
•
•
19-27.
SATA Controller
19-29
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