MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 342
MPC8536DS
Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(1706 pages)
3.MPC8536DS.pdf
(2 pages)
4.MPC8536DS.pdf
(126 pages)
Specifications of MPC8536DS
Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8536EBVTAVLA PDF datasheet
- MPC8536EBVTAVLA PDF datasheet #2
- MPC8536DS PDF datasheet #3
- MPC8536DS PDF datasheet #4
- Current page: 342 of 1706
- Download datasheet (15Mb)
14 x 10
14 x 10
DDR Memory Controller
Chip select interleaving is supported for the memory controller, and is programmed in
DDR_SDRAM_CFG[BA_INTLV_CTL]. Interleaving is supported between chip selects 0 and 1 or chip
selects 2 and 3. In addition, interleaving between all four chip selects can be enabled. When interleaving
is enabled, the chip selects being interleaved must use the same size of memory. If two chip selects are
interleaved, then 1 extra bit in the address decode is used for the interleaving to determine which chip
select to access. If four chip selects are interleaved, then two extra bits are required in the address decode.
Table 8-57
Table 8-58
8-68
Table 8-56. DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving and Partial Array Self Refresh
10 x 3
10 x 2
10 x 3
10 x 2
9 x 2
x 3
x 2
14 x
14 x
13 x
13 x
13 x
Row
Col
Row
Col
x
x
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MBA
MBA
MBA
MBA
MBA
MBA
MBA
Table 8-57. Example of Address Multiplexing for 64-Bit Data Bus Interleaving between
illustrates examples of address decode when interleaving between two chip selects, and
shows examples of address decode when interleaving between four chip selects.
msb
msb
4
4
13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34–35
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
13 12 11 10 9 8 7 6 5 4 3 2 1
13 12 11 10 9 8 7 6 5 4 3 2 1 0
13 12 11 10 9 8 7 6 5 4 3 2 1 0
12 11 10 9
Two Banks with Partial Array Self Refresh Disabled
12 11 10 9
12 11 10 9
8
7
8
Disabled (continued)
6
7
8
Address from Core Master
5
6
7
Address from Core Master
4
5
6
3
4
5
2
3
4
SEL
1
2
3
CS
0
0
1
2
SEL
CS
20 21 22 23 24 25 26 27 28 29 30 31 32 33–35
2 1 0
2
0
1
2
1 0
1
1
0
1 0
1 0
0
0
1
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
9
9
0
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
8
8
8
7
7
7
6
6
6
5
5
5
Freescale Semiconductor
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
lsb
lsb
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