MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1533

BOARD DEV SYSTEM MPC8536E

MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8536DS

Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
23.4.1.31 SerDes2 Control Register 1 (SRDS2CR1)
Shown in
Individual lanes can be powered down using SRDS2CR1[0] and SRDS2CR1[4]. It requires the entire
SerDes2 to reset in order to activate a lane from powering down.
Table 23-34
Freescale Semiconductor
Offset 0xE_3104
Reset
Reset
Bits
1–3
5–7
W
W
R
R
0
4
8
9
PDA
16
0
0
Figure
17
0
1
describes the fields of SRDS2CR1.
IPSEN
Name
PDE
PDA
PPSEN
23-31, the SRDS2CR1 contains the functional control bits for the SerDes2 logic.
18
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Lane A power down
0) Normal
1) Power down Lane A
Recommended setting per protocol:
SGMII: 0
SATA: 0
Reserved
Lane E power down
0) Normal
1) Power down Lane E
Recommended setting per protocol:
SGMII: 0
SATA: 0
Reserved
Internal power save enable
0 SerDes power saving disabled
1 SerDes power saving enabled (recommended)
Reserved
19
0
3
Figure 23-31. SerDes2 Control Register 1 (SRDS2CR1)
PDE
20
0
4
Table 23-34. SRDS2CR1 Field Descriptions
21
0
5
0
0
7
IPSEN
24
0
8
All zeros
Description
25
1
9
X3SA
10
26
0
11
27
0
28
0
Access: Read/Write
13
29
0
Global Utilities
X3SE
14
30
0
23-41
15
31
0

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