MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 865

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 14-105
Table 14-109
Freescale Semiconductor
Reset
Reset
Offse
20–22
8–15
Bits
0–7
16
17
18
19
23
24
25
W
W
R
R
t
eTSEC1:0x2_4A00;
eTSEC3:0x2_6A00
RRX
16
0
0
0
Name
RRX
RXE
RFC
RTX
TXE
LPB
TFC
IPG
—
—
RTX
17
describes the fields of the FIFOCFG register.
0
0
describes the definition for the FIFOCFG register.
Reserved
Minimum inter packet gap. This sets the minimum number of cycles inserted between back-to-back frames
transmitted over the FIFO interface. The minimum required is 3 cycles if CRCAPP=0 and 7 cycles for 8-bit
interfaces if CRCAPP=1.
Enable reset of FIFO receive function.
0 Do not reset the FIFO receiver.
1 Reset the FIFO receiver for as long as this bit is set.
Enable reset of FIFO transmit function.
0 Do not reset the FIFO transmitter.
1 Reset the FIFO transmitter for as long as this bit is set.
Enable FIFO receive function.
0 Disable reception over the FIFO interface, ignoring data presented to the signals.
1 Enable normal reception over the FIFO interface.
Enable FIFO transmit function.
0 Disable transmission over the FIFO interface.
1 Enable normal transmission over the FIFO interface.
Reserved.
Loopback enable.
0 Do not loopback data in the FIFO interface.
1 Loopback transmitted data to the FIFO receiver rather than outputting transmitted data to signals.
Enable receive flow control. Setting FFC overrides this bit.
0 Do not allow the FIFO receiver to assert link-level flow control if eTSEC requires it.
1 Allow the FIFO receiver to assert link-level flow control if eTSEC requires it. This is the default setting.
Enable transmit flow control.
0 Do not allow the FIFO transmitter to assert link-level flow control if transmit data is unavailable, resulting
1 Allow the FIFO transmitter to assert link-level flow control if transmit data is unavailable and SIGM = 01.
RXE
18
in underruns.
This is the default setting.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
TXE
19
0
0
—
Figure 14-105. FIFOCFG Register Definition
20
0
0
Table 14-109. FIFOCFG Field Descriptions
—
0
0
22
0
0
LPB
23
0
0
7
RFC
24
0
1
8
Description
TFC
25
0
1
FFC CRCAPP CRCCHK
26
0
0
Enhanced Three-Speed Ethernet Controllers
27
0
0
IPG
28
0
0
Access: Read/Write
—
29
0
0
30
0
0
SIGM
14-117
15
31
0
0