MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 243

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-18
Figure 6-22
Table 6-19
Freescale Semiconductor
Offset 0x2_0E4C
Reset
0–26
Bits
Bits
0–1
2–3
5–7
27
28
29
30
31
4
W
R
0 1
— DWNUM — TRANSSIZ BURST — TRANSSRC
MBECCINTEN
SBECCINTEN
L2CFGINTEN
TPARINTEN
TRANSSIZ
DWNUM
describes L2ERRINTEN fields.
describes L2ERRATTR fields.
2
Name
Name
shows the L2 error attributes capture register (L2ERRATTR).
—
—
—
—
3
4
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 6-22. L2 Error Attributes Capture Register (L2ERRATTR)
Reserved
Double-word number of the detected error (data ECC errors only)
Reserved
Transaction size for detected error
000 8 bytes
001 1 byte
010 2 bytes
011 3 bytes
5
Reserved
Tag parity error reporting enable
0 Tag parity error reporting disabled
1 Tag parity error reporting enabled
Multiple-bit ECC error reporting enable. Note that uncorrectable read errors may cause the
assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it
is disabled (by clearing HID1[RFXE]). If RFXE is zero and this error occurs,
L2ERRDIS[MBECCDIS] must be cleared and MBECCINTEN must be set to ensure that an
interrupt is generated. For more information, see the reference manual for the e500 core.
0 Multiple-bit ECC error reporting disabled
1 Multiple-bit ECC error reporting enabled
Single-bit ECC error reporting enable
0 Single-bit ECC error reporting disabled
1 Single-bit ECC error reporting enabled
Reserved
L2 configuration error reporting enable
0 L2 configuration error reporting disabled
1 L2 configuration error reporting enabled
Single-beat
7
Table 6-18. L2ERRINTEN Field Descriptions
Table 6-19. L2ERRATTR Field Descriptions
8
9 10 11
Burst
Reserved
16 bytes
32 bytes
Reserved
All zeros
15 16 17
—
Description
Description
TRANSTYPE
18
100 4 bytes
101 5 bytes
110 6 bytes
111 7 bytes
19
Single-beat
20
L2 Look-Aside Cache/SRAM
—
Burst
Reserved
Reserved
Reserved
Reserved
Access: Read/Write
30
VALINFO
31
6-23