MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 510

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
AESU Mode Register Auxiliary Bit Settings for GCM Cipher Modes
Table 10-32
different operating conditions.
AUX0 has different use depending on whether encryption or decryption is specified. For decryption, it
determines whether the provided key should be first unrolled before processing starts, while in case of
encryption it should generally be set to 0 unless GCM-GHASH cipher mode is desired. AUX2 determines
whether the final MAC tag is to be computed or not. If AUX2 is set to 1, E(K, Y
the GHASH(H, AAD, ciphertext) is going to be performed and then XORed to give the MAC tag. Hence,
if the message is split into multiple descriptors, only the last one should have AUX2=1 for proper MAC
tag computation. AUX1 is used to resolve the issues related to the splitting of messages into multiple
descriptors.
general, whenever the final GHASH iteration needs to be computed (either for GHASH(H, {}, IV) or
GHASH(H, AAD, ciphertext)), and the current length is not equal to total length for either IV, AAD, or
text data, then AUX1 should be set to 1. Consequently, an AUX1 value of 1 also indicates that the context
registers 9-10 need to provide the total length of IV, AAD, or text data for this to be accomplished.
10-80
Table 10-32
shows the significance of the AUX bits (bits 58–60) in the AESU mode register, under
AUX0 (bit 60) and Encrypt
AUX0 (bit 60) and Decrypt
AUX2 (bit 58)
AUX1 (bit 59)
Auxiliary Bit
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
shows the proper settings of AUX1 for several scenarios of message splitting. In
Table 10-32. GCM Cipher Mode Auxiliary Bit Definitions
Do not compute MAC
One of the following cases:
Descriptor contains the whole
message (IV+AAD+text data)
Descriptor contains the whole IV
and no or part of AAD or text
data
Descriptor contains a non-final
part of IV, AAD, text data (IV,
AAD or text data split between
descriptors)
Descriptor contains the final part
of AAD or text data but no MAC
is computed
--
The key is to be unrolled
0
Definitions
Compute MAC
One of the following cases:
Descriptor contains the final part
of IV (IV split between
descriptors)—len(IV)
Descriptor contains the final part
of text data and the final MAC is
computed (AUX2=1) (text data
split between
descriptors)—len(AAD)
len(text data)
Descriptor contains the whole
text data but no or part of AAD
and the final MAC is
computed—len(AAD)
data)
Descriptor contains the final part
of AAD and the final MAC is
computed—len(AAD)
data)
Descriptor computes only MAC
(based on restored context) but
does not contain either IV, AAD
or text data —len(AAD)
data)
GHASH-only mode
The key is already unrolled
T
T
T
needed
needed
needed
T
needed
1
0
) and the last iteration of
T
T
T
Freescale Semiconductor
, len(text
, len(text
needed
T
T
, len(text
,