MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 897

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

connection with a PHY. The RGMII is implemented as defined by the RGMII specification Version 1.2a
9/22/00.
14.6.1.5
This section describes the ten-bit interface (TBI) intended to be used between the PHYs and the eTSEC to
implement a standard SerDes interface for optical-fiber devices in 1000BASE-SX/LX applications.
Figure 14-136
module connection with a PHY. RBC0 and RBC1 are differential 62.5 MHz receive clocks. If not
connected to the TBI PHY, the Signal Detect (SDET) input must be tied high. This causes the eTSEC to
begin auto negotiation with the SERDES immediately upon the TBI module being enabled.
Freescale Semiconductor
1
The management signals (MDC and MDIO) are common to all of the gigabit Ethernet controllers module
connections in the system, assuming that each PHY has a different management address.
eTSEC
Ten-Bit Interface (TBI)
depicts the basic components of the TBI including the signals required to establish eTSEC
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Transmit Data (TSECn_TXD[3:0]/TSECn_TXD[7:4])
Receive Data (TSECn_RXD[3:0]/TSECn_RXD[7:4])
Transmit Control (TX_EN/f(TX_EN,TX_ER))
Receive Control (RX_DV/f(RX_DV,RX_ER))
Gigabit Transmit Clock (TSEC n _GTX_CLK)
Gigabit Reference Clock (GTX_CLK125)
Figure 14-135. eTSEC-RGMII Connection
Receive Clock (TSEC n _RX_CLK)
Management Data Clock
Management Data I/O
1
1
(MDIO)
(MDC)
Enhanced Three-Speed Ethernet Controllers
Ethernet
Gigabit
PHY
Medium
14-149