MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 469

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
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MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-11. Channel Configuration Register Fields (continued)
Reset channel
0 No special action.
1 Causes a software reset of the channel. All channel registers are cleared. Other actions
After the reset sequence is complete, the channel returns to the idle state, the R bit is
cleared automatically, and normal operation is resumed.
Reserved, should be set to zero.
Fast clock counting.
0 Watchdog timer counts normally
1 Watchdog timer counts in an accelerated fashion (force-assert several selected bits in
Watchdog go now.
0 Watchdog timer disabled
1 Watchdog timer enabled
Permit byte summing.
0 Bytes written to EU input FIFOs and read from EU output FIFOs are not counted in the
1 Bytes written to EU input FIFOs and read from EU output FIFOs are counted in the data
Reserved, should be set to zero.
Burst size. The SEC accesses long text-parcels in main memory through bursts of
programmable size.
0 Burst size is 64 bytes
1 Burst size is 128 bytes
ICV writeback status enable.
0 No special action.
1 If the descriptor calls for ICV checking, then at the completion of descriptor processing,
Reserved, should be set to zero.
or a 32-bit address bus.
0 Channel’s address bus is 32 bits.
1 Channel’s address bus is 36 bits.
Channel done writeback enable.
0 Channel done writeback disabled.
1 Channel done writeback enabled. Upon successful completion of descriptor processing,
Extend address enable. This bit determines whether the channel uses a 36-bit address bus
• If the R bit is set while the channel is requesting an EU assignment from the controller,
• If the R bit is set after the channel has been assigned one or more EUs, the channel
depend on the state of the channel when the bit is set:
then the channel cancels its request.
requests a write from the controller to set the software reset bit of each reserved EU. The
channel then releases the EU(s).
timer) to assist with functional testing.
data bytes counters
bytes counters
the channel writes back to the descriptor header the DONE, ICCR0, and ICCR1 fields
(see
if the NT bit is cleared (for global notification), or if the DN (done notification) bit is set in
the header word of the descriptor, then the channel notifies the host by writing back the
descriptor header with the DONE field shown in
the memory location of the original descriptor header to determine if that descriptor has
been completed.
Table
10-5).
1
.
2
2
Description
Table
10-5. This enables the host to poll
Security Engine (SEC) 3.0
10-39