MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1521
MPC8536DS
Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(1706 pages)
3.MPC8536DS.pdf
(2 pages)
4.MPC8536DS.pdf
(126 pages)
Specifications of MPC8536DS
Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8536EBVTAVLA PDF datasheet
- MPC8536EBVTAVLA PDF datasheet #2
- MPC8536DS PDF datasheet #3
- MPC8536DS PDF datasheet #4
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Table 23-22
23.4.1.20 Processor Version Register (PVR)
Shown in
of the PVR in the e500 core (and is therefore accessible to external devices).
Version Register (PVR) and System Version Register (SVR),”
MPC8536E.
Freescale Semiconductor
Offset 0x0A0
Reset
W
R
13–15
17–19
21–31
9–11
Bits
1–3
5–7
12
16
20
0
4
8
0
Figure
describes the bit settings of AUTORSTSR.
RST_CKSTP
RST_DPSLP
RST_CORE
RST_MPIC
RST_WRS
READY
Name
23-20, the PVR contains the e500 processor version number. It is a memory-mapped copy
—
—
—
—
—
—
See
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 5.3.1, “Processor Version Register (PVR) and System Version Register (SVR)
Core was reset in response to check stop
0 No reset
1 Reset occurred.
Reserved
Core was reset in respone to watchdog timer expiration
0 No reset
1 Reset occurred
Reserved
Core was reset in respone to MPIC reset request
0 No reset
1 Reset occurred
Reserved
Core was reset in respone to internal core request to reset itself by seeting bit DBCR[RST]
register.
0 No reset
1 Reset occurred
Reserved
Core ready pin. This bit reflects what is driven on the READY_P external signal.
0 Core not ready
1 Core ready
Reserved
Core was reset in respone to deep sleep by seeting bit POWMGTCSR[DPSLP] register
0 No reset
1 Reset occurred
Reserved
Version
Figure 23-20. Processor Version Register (PVR)
Table 23-22. AUTORSTSR Field Descriptions
15 16
Description
lists the complete values for the
Revision
Section 5.3.1, “Processor
Access: Read only
Global Utilities
23-29
31
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