MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1090

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
The PCI controller also provides a direct way to generate PCI interrupt-acknowledge transactions. Reads
from PCI INT_ACK at offset 0x008 generate PCI interrupt-acknowledge transactions. Note that processor
writes to these addresses do nothing.
16.4.2.12.2 Special-Cycle Transactions
The special-cycle command provides a mechanism to broadcast select messages to all devices on the PCI
bus. The special-cycle command contains no explicit destination address but is broadcast to all PCI agents.
When the PCI controller detects a write to PCI CFG_DATA, it checks the enable flag and the device
number in PCI CFG_ADDR. If the enable bit is set, the bus number corresponds to the local PCI bus (bus
number = 0x00), the device number is all ones (0b1_1111), the function number is all ones (0b111), and
the register number is zero (0b00_0000), then the PCI controller performs a special-cycle transaction on
the local PCI bus. If the bus number indicates a nonlocal PCI bus, the PCI controller performs a type 1
configuration cycle translation, similar to any other configuration cycle for which the bus number does not
match.
Aside from the special-cycle command (PCI_C/BE[3:0] = 0b0001) the address phase contains no other
valid information. Although there is no explicit address, PCI_AD[31:0] are driven to a stable state, and
parity is generated. During the data phase, PCI_AD[31:0] contain the special-cycle message and an
optional data field. The special-cycle message is encoded on the 16 least-significant bits (PCI_AD[15:0]);
the optional data field is encoded on the most-significant 16 lines (PCI_AD[31:16]). The special-cycle
message encodings are assigned by the PCI SIG steering committee. The current list of defined encodings
are provided in
Note that the PCI controller does not automatically issue a special-cycle message when it enters any of its
power-saving modes. It is the responsibility of software to issue the appropriate special-cycle message, if
needed.
Each receiving agent must determine whether the special-cycle message is applicable to itself. Assertion
of PCI_DEVSEL in response to a special-cycle command is not necessary. The initiator of the
special-cycle transaction can insert wait states but since there is no specific target, the special-cycle
message and optional data field are valid on the first clock PCI_IRDY is asserted. All special-cycle
transactions are terminated by master-abort; however, the master-abort bit in the initiator’s bus status
register is not set for special-cycle terminations.
16-64
Table
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
16-51.
Table 16-51. Special-Cycle Message Encodings
0x0003–0xFFFF
PCI_AD[15:0]
0x0000
0x0001
0x0002
SHUTDOWN
HALT
x86 architecture-specific
—
Message
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