MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 290
MPC8536DS
Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(1706 pages)
3.MPC8536DS.pdf
(2 pages)
4.MPC8536DS.pdf
(126 pages)
Specifications of MPC8536DS
Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8536EBVTAVLA PDF datasheet
- MPC8536EBVTAVLA PDF datasheet #2
- MPC8536DS PDF datasheet #3
- MPC8536DS PDF datasheet #4
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- Download datasheet (15Mb)
DDR Memory Controller
8.4.1.4
DDR SDRAM timing configuration register 3, shown in
time, which is combined with TIMING_CFG_1[REFREC] to determine the full refresh recovery time.
Table 8-9
8-16
Offset 0x100
Reset
12–15
16–18
8–11
Bits
0–6
7
W
R
0
EXT_ACTTOPRE Extended Activate to precharge interval (t
EXT_REFREC
—
describes TIMING_CFG_3 fields.
Name
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)
—
—
—
6
EXT_ACTTOPRE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 8-5. DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)
7
Reserved, should be cleared.
activate command until a precharge command is allowed. This field is concatenated with
TIMING_CFG_1[ACTTOPRE] to obtain a 5-bit value for the total activate to precharge. Note that a
5-bit value of 0_0000 is the same as a 5-bit value of 1_0000. Both values represent 16 cycles.
0
Reserved, should be cleared.
Extended refresh recovery time (t
until an activate command is allowed. This field is concatenated with TIMING_CFG_1[REFREC] to
obtain an 8-bit value for the total refresh recovery. Note that hardware adds an additional 8 clock
cycles to the final, 8-bit value of the refresh recovery. t
that t
0000 0 clocks
0001 16 clocks
0010 32 clocks
0011 48 clocks
0100 64 clocks
0101 80 clocks
0110 96 clocks
0111 112 clocks
Reserved, should be cleared.
RFC
0 clocks
Table 8-9. TIMING_CFG_3 Field Descriptions
is calculated as follows:
8
—
11 12
EXT_REFREC
RFC
All zeros
). Controls the number of clock cycles from a refresh command
15 16
Figure
RAS
Description
—
). Determines the number of clock cycles from an
18
8-5, sets the extended refresh recovery
1
1000 128 clocks
1001 144 clocks
1010 160 clocks
1011 176 clocks
1100 192 clocks
1101 208 clocks
1110 224 clocks
1111 240 clocks
EXT_CASLAT
RFC
16 clocks
19
= {EXT_REFREC || REFREC} + 8, such
20
Freescale Semiconductor
—
Access: Read/Write
28 29
CNTL_ADJ
31
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