MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1133
MPC8536DS
Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(1706 pages)
3.MPC8536DS.pdf
(2 pages)
4.MPC8536DS.pdf
(126 pages)
Specifications of MPC8536DS
Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.3.6.5.1
PEX_ERR_CAP_R0 for the case when the error is caused by an outbound transaction from an internal
source (that is, PEX_ERR_CAP_STAT[GSID]
PEX_CONFIG_ADDR/PEX_CONFIG_DATA access, is shown in
Table 17-27
caused by an outbound transaction from an internal source.
17.3.6.5.2
PEX_ERR_CAP_R0 for the case when the error is caused by an inbound transaction from an external
source (that is, PEX_ERR_CAP_STAT[GSID] = 0h02 for controller 1), is shown in
Table 17-28
inbound transaction from an external source.
Freescale Semiconductor
Offset 0xE28
Reset
Offset 0xE28
Reset
W
W
R
R
0
18–22
23–31
16-17
0
0–15
Bits
describes the fields of the PCI Express error capture register 0 for the case when the error is
describes the fields of PEX_ERR_CAP_R0 for the case when the error is caused by an
PEX_ERR_CAP_R0—Outbound Case
PEX_ERR_CAP_R0—Inbound Case
Figure 17-28. PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
Figure 17-29. PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
Table 17-27. PCI Express Error Capture Register 0 Field Descriptions
Name
TYPE
FMT
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
—
Reserved
PCI Express format. This field indicates the PCI Express packet format. See PCI
Express Spec 1.0a for more information on 3 or 4 DW (4-byte) header format.
PCI Express type. This field indicates the PCI express packet type. See PCI Express
Spec 1.0a for more information on 3 or 4 DW (4-byte) header format.
Reserved
—
Internal Source, Outbound Transaction
Internal Source, Outbound Transaction
External Source, Inbound Transaction
0h02 ) and the error is due to timeout condition or
All zeros
All zeros
15 16 17 18
GH0
Description
FMT
Figure
TYPE
17-28.
22 23
PCI Express Interface Controller
Figure
Access: Read/Write
Access: Read/Write
—
17-29.
17-37
31
31
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