MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 977
MPC8536DS
Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(1706 pages)
3.MPC8536DS.pdf
(2 pages)
4.MPC8536DS.pdf
(126 pages)
Specifications of MPC8536DS
Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 14-187
Table 14-188
Freescale Semiconductor
Set source clock divide by 14, for example, to insure that TSEC_MDC clock speed is not greater than 2.5 MHz.
ECGTX_CLK125
Set up the MII Mgmt for a read cycle to TBI’s Control register (write the TBI’s address and Register address),
eTSEC Signals
MDIO
MDC
Sum
describes the shared signals for the RTBI interface.
describes the register initializations required to configure the eTSEC in RTBI mode.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I/O
I/O
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
O
Table 14-188. RTBI Mode Register Initialization Steps
I
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
The control register (CR) is at offset address 0x0 from TBIPA.
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
Signals
No. of
This indicates that the eTSEC MII Mgmt bus is idle.
1
1
3
1
Table 14-187. Shared RTBI Signals
(This example has Statistics Enable = 1)
Assign a Physical address to the TBI,
Setup the MII Mgmt clock speed,
to 02608C:876543, for example.
to 02608C:876543, for example.
Initialize MAC Station Address,
Initialize MAC Station Address,
(I/F Mode = 2, Full Duplex = 1)
GTX_CLK125
GMII Signals
set to 16, for example.
Initialize MACCFG2,
MDIO
MDC
Sum
Initialize ECNTRL,
Clear Soft_Reset,
Set Soft_Reset,
I/O
I/O
O
I
Signals
No. of
1
1
1
3
Enhanced Three-Speed Ethernet Controllers
Management interface clock
Management interface I/O
Reference clock
Function
14-229
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