MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1291
MPC8536DS
Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(1706 pages)
3.MPC8536DS.pdf
(2 pages)
4.MPC8536DS.pdf
(126 pages)
Specifications of MPC8536DS
Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8536EBVTAVLA PDF datasheet
- MPC8536EBVTAVLA PDF datasheet #2
- MPC8536DS PDF datasheet #3
- MPC8536DS PDF datasheet #4
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- Download datasheet (15Mb)
20.4.8
The protocol control register is shown in
Freescale Semiconductor
Offset: 0x028 (PROCTL)
WECRM
WECINS
WECINT
Reset
Reset
Field
8–12
0–4
5
6
7
W
W
R
R
16
0
0
0
Protocol Control Register (PROCTL)
Reserved
Wake-up event enable on SD card removal. This bit enables wakeup event via card removal assertion in the
IRQSTAT register. FN_WUS (wake-up support) in CIS does not affect this bit.
0 Disable
1 Enable
Wake-up event enable on SD card insertion. This bit enables wakeup event via card insertion assertion in the
IRQSTAT register. FN_WUS (wake-up support) in CIS does not affect this bit.
0 Disable
1 Enable
Wake-up event enable on card interrupt. This bit enables wakeup event via card interrupt assertion in the
IRQSTAT register. This bit can be set to 1 if FN_WUS (wake-up support) in CIS is set to 1.
0 Disable
1 Enable
Reserved
The host driver can issue CMD0, CMD12, CMD13 (for memory) when the
SDHC_DAT lines are busy during a data transfer. These commands can be
issued when PRSSTAT[CIHB] is cleared. Other commands should be
issued when PRSSTAT[CDIHB] is cleared. Possible changes to the SD
physical specification may add other commands to this list in the future.
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
0
0
Figure 20-10. Protocol Control Register (PROCTL)
0
0
—
Table 20-12. PROCTL Field Descriptions
4
0
0
CRM
WE
0
0
5
Figure
CINS
WE
0
0
6
20-10.
NOTE
CINT
WE
23
Description
0
0
7
CDSS CDTL
24
0
0
8
25
0
0
—
26
0
1
EMODE
Enhanced Secure Digital Host Controller
11
27
0
0
D3CD
12
28
0
0
CTL
Access: Read/Write
RW
13
29
0
0
DTW
CREQ
14
30
0
0
SABG
20-17
REQ
—
15
31
0
0
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