MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 758

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14-10
TSEC n _GTX_CLK
TSEC n _CRS
TSEC n _COL
Signal
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
I/O
O
O
I
I
Table 14-2. eTSEC Signals—Detailed Signal Descriptions
Collision input. The behavior of this signal is not specified while in full-duplex mode.
Carrier sense input. In TBI and RTBI modes, this signal is used as SDET (signal detect).In TBI
mode SDET must be tied high externally on the board. In RTBI mode SDET is tied high internally.
This signal is not used in the following modes:
Receiver flow control signal in FIFO mode.
This signal is not used in the eTSEC Ethernet modes.
Gigabit transmit clock. This signal is an output from the eTSEC into the PHY. TSEC n _GTX_CLK
is a 125-MHz clock that provides a timing reference for TX_EN, TXD, and TX_ER in the following
modes:
In RGMII mode, TSEC n _GTX_CLK becomes the transmit clock and provides timing reference
during 1000Base-T (125 MHz), 100Base-T (25 MHz) and 10Base-T (2.5 MHz) transmissions.
This signal feeds back the uninverted transmit clock in MII or FIFO modes, but feeds back an
inverted transmit clock in RTBI or RGMII modes.
This signal is driven low unless transmission is enabled, or the eTSEC is in TBI or FIFO mode.
Meaning
Meaning
Meaning
• RMII
• GMII
• RGMII
• GMII
• TBI
• RTBI
Timing Asserted/Negated—This signal is not required to transition synchronously with
Timing Asserted/Negated—This signal is not required to transition synchronously with
Timing Asserted/Negated—This signal transitions synchronously with TSEC n _RX_CLK.
State
State
State
Asserted/Negated—In MII mode, this signal is asserted upon detection of a collision,
This signal is not used in the following modes:
Asserted/Negated—In MII mode, TSEC n _CRS is asserted while the transmit or
Asserted/Negated—TSEC n _CRS is asserted while the FIFO receiver is unprepared to
• RMII
• GMII
• TBI
• RTBI
• RGMII
and must remain asserted while the collision persists. In FIFO mode this signal
is used to effect flow control on the transmitter.
TSEC n _TX_CLK or TSEC n _RX_CLK.
receive medium is not idle. In the event of a collision, TSEC n _CRS must remain
asserted for the duration of the collision.
TSEC n _TX_CLK or TSEC n _RX_CLK.
accept additional receive data.
Description
Freescale Semiconductor