MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 47

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

At recommended operating conditions with L/TV
Figure 19
2.9.2.3.2
Table 31
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
1. The symbols used for timing specifications herein follow the pattern of t
Figure 20
Freescale Semiconductor
for inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,
the subscript of t
appropriate letter: R (rise) or F (fall).
provides the MII receive AC timing specifications.
provides the AC test load for eTSEC.
shows the MII transmit AC timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
MII Receive AC Timing Specifications
Parameter/Condition
MRX
TXD[3:0]
TX_CLK
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
TX_EN
TX_ER
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
Output
Table 31. MII Receive AC Timing Specifications
MRX
Figure 19. MII Transmit AC Timing Diagram
t
MTXH
clock reference (K) going to the low (L) state or hold time. Note that, in general, the
MRDXKL
DD
Figure 20. eTSEC AC Test Load
of 3.3 V ± 5%.
t
MTX
Z
0
symbolizes MII receive timing (GR) with respect to the time data input signals
= 50 Ω
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
t
t
MTKHDX
Symbol
MRXH
t
t
t
MTXF
MRDVKH
MRDXKH
t
t
t
t
MRXR
MRXF
MRX
MRX
/t
for outputs. For example, t
MRX
(first two letters of functional block)(signal)(state) (reference)(state)
1
R
t
L
MTXR
= 50 Ω
10.0
10.0
Min
1.0
1.0
—
—
35
LV
DD
Typ
400
MRDVKH
40
—
—
—
—
—
/2
MRX
clock reference (K) going
symbolizes MII receive
Max
4.0
4.0
65
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
%
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