MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 70

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except LAD/LDP
and LALE)
Local bus clock to output high impedance for LAD/LDP
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
6. t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
enhanced Local Bus Controller (eLBC)
Figure 38
70
for inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one(1). Also, t
output (O) going invalid (X) or output hold time.
bypass mode to 0.4 × BV
the component pin is less than or equal to the leakage current specification.
with LBCR[AHD] = 0.
complementary signals at BV
LBOTOT
provides the AC test load for the local bus.
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
Table 53. Local Bus General Timing Parameters (BV
(First two letters of functional block)(reference)(state)(signal)(state)
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
LBKHOX
Parameter
DD
Output
symbolizes local bus timing (LB) for the t
of the signal in question for 1.8-V signaling levels.
DD
/2.
DD
/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
Figure 38. Local Bus AC Test Load
Z
0
= 50 Ω
Configuration Symbol
—
—
—
LBK
for outputs. For example, t
(First two letters of functional block)(signal)(state) (reference)(state)
LBK
clock reference (K) to go high (H), with respect to the
R
clock reference (K) goes high (H), in this case for
L
t
t
t
DD
LBKHOX2
LBKHOZ1
LBKHOZ2
= 50 Ω
= 1.8 V DC) (continued)
1
BV
Min
0.9
—
—
DD
/2
LBIXKH1
Max
Freescale Semiconductor
2.6
2.6
—
symbolizes local bus
LBOTOT
Unit
ns
ns
ns
is guaranteed
Notes
3
5
5