DEMO9S08JM16 Freescale Semiconductor, DEMO9S08JM16 Datasheet - Page 68

• Manufacturer Part Number: DEMO9S08JM16
• Description: BOARD DEMO FOR JM16 FAMI
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08JM16

• Contents: Board with Daughter card, Cable, Documentation, Mini-AB USB Kit
• Processor To Be Evaluated: MC9S08JM16
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: Flexis - S08JM
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08JM16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Resets, Interrupts, and System Configuration
5.6.3
When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE
set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur.
5.6.4
The LVD system has a low voltage warning flag to indicate the user that the supply voltage is approaching,
but is still above, the LVD voltage. The LVW does not have an interrupt associated with it. There are two
user selectable trip voltages for the LVW, one high (V
selected by LVWV in SPMSC2.
5.7
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in
address assignments for all registers. This section refers to registers and control bits only by their names.
A Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of
5.7.1
This direct-page register includes status and control bits, which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
68
Reset
W
R
Reset, Interrupt, and System Control Registers and Control Bits
LVD Interrupt Operation
Low-Voltage Warning (LVW)
Interrupt Pin Request Status and Control Register (IRQSC)
0
0
7
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
= Unimplemented or Reserved
Operation.”
IRQPDD
0
6
IRQEDG
MC9S08JM16 Series Data Sheet, Rev. 2
0
5
Chapter 4,
IRQPE
0
4
LVWH
“Memory,” of this data sheet for the absolute
) and one low (V
IRQF
3
0
IRQACK
0
0
2
LVWL
). The trip voltage is
Freescale Semiconductor
IRQIE
0
1
IRQMOD
0
0