DEMO9S08JM16 Freescale Semiconductor, DEMO9S08JM16 Datasheet - Page 81

• Manufacturer Part Number: DEMO9S08JM16
• Description: BOARD DEMO FOR JM16 FAMI
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08JM16

• Contents: Board with Daughter card, Cable, Documentation, Mini-AB USB Kit
• Processor To Be Evaluated: MC9S08JM16
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: Flexis - S08JM
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08JM16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.5.2
In addition to the I/O control, port A pins are controlled by the registers listed below.
Freescale Semiconductor
PTAPE[5,0]
PTASE[5,0]
Reset
Reset
Reset
Field
Field
5,0
5,0
W
W
W
R
R
R
Port A Pin Control Registers (PTAPE, PTASE, PTADS)
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
0
0
0
7
7
7
Figure 6-5. Output Slew Rate Control Enable for Port A (PTASE)
Figure 6-6. Output Drive Strength Selection for Port A (PTASE)
0
0
0
6
6
6
Figure 6-4. Internal Pullup Enable for Port A (PTAPE)
Table 6-3. PTADD Register Field Descriptions
Table 6-4. PTASE Register Field Descriptions
PTAPE5
PTASE5
PTADS5
MC9S08JM16 Series Data Sheet, Rev. 2
0
1
0
5
5
5
0
1
0
4
4
4
Description
Description
3
0
3
1
3
0
0
1
0
2
2
2
Chapter 6 Parallel Input/Output
0
1
0
1
1
1
PTAPE0
PTASE0
PTADS0
0
1
0
0
0
0
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