PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 207

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.0
All members of the PIC18F97J60 family of devices
feature an embedded Ethernet controller module. This
is a complete connectivity solution, including full imple-
mentations of both Media Access Control (MAC) and
Physical Layer transceiver (PHY) modules. Two pulse
transformers and a few passive components are all that
are required to connect the microcontroller directly to
an Ethernet network.
The Ethernet module meets all of the IEEE 802.3
specifications
twisted-pair network. It incorporates a number of
packet filtering schemes to limit incoming packets. It
also provides an internal DMA module for fast data
throughput and hardware assisted IP checksum calcu-
lations. Provisions are also made for two LED outputs
to indicate link and network activity.
A simple block diagram of the module is shown in
Figure 18-1.
FIGURE 18-1:
© 2007 Microchip Technology Inc.
Ethernet RAM
8-Kbyte
Buffer
ETHERNET MODULE
Ethernet
Buffer
Addresses
Buffer Pointers
for
Ethernet
10-BaseT
ETHERNET MODULE BLOCK DIAGRAM
Microcontroller SFRs
Arbiter
Ethernet
Data
ch2
ch0
ch1
EDATA
connectivity
8
MIRD/MIWR
MIREGADR
Ethernet
to
Control
Preliminary
a
ch0
ch1
Host Interface
IP Checksum
Flow Control
RXF (Filter)
DMA and
PIC18F97J60 FAMILY
RXBM
TXBM
The Ethernet module consists of five major functional
blocks:
1.
2.
3.
4.
5.
PHY Register Data
PHY Register Addresses
RX
TX
The PHY transceiver module that encodes and
decodes the analog data that is present on the
twisted-pair interface and sends or receives it
over the network.
The MAC module that implements IEEE 802.3
compliant MAC logic and provides Media
Independent Interface Management (MIIM) to
control the PHY.
An independent, 8-Kbyte RAM buffer for storing
packets that have been received and packets
that are to be transmitted.
An arbiter to control access to the RAM buffer
when requests are made from the microcontroller
core, DMA, transmit and receive blocks.
The register interface that functions as an inter-
preter of commands and internal status signals
between the module and the microcontroller’s
SFRs.
Microcontroller Data Bus
LEDA/LEDB Control
MAC
Interface
Interface
MIIM
MII
DS39762C-page 205
PHY
RX
TX
TPOUT+
TPOUT-
RBIAS
TPIN+
TPIN-