PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 215

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.2.2
Like other peripherals, direct control of the Ethernet
module is accomplished through a set of SFRs.
Because of their large number, the majority of these
registers are located in the bottom half of Bank 14 of
the microcontroller’s data memory space.
Five key SFRs for the Ethernet module are located in
the microcontroller’s regular SFR area in Bank 15,
where fast access is possible. They are:
• ECON1
• EDATA
• EIR
• The Ethernet Buffer Read Pointer pair (ERDPTH
ECON1 is described along with other Ethernet control
registers in the following section. EDATA and
ERDPTH:ERDPTL are the Ethernet Data Buffer
registers and its pointers during read operations (see
Section 18.2.1 “Ethernet Buffer and Buffer Pointer
Registers”). EIR is part of the Ethernet interrupt
structure and is described in Section 18.3 “Ethernet
Interrupts”.
REGISTER 18-1:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
and ERDPTL)
TXRST
R/W-0
SFRs AND THE ETHERNET
MODULE
TXRST: Transmit Logic Reset bit
1 = Transmit logic is held in Reset
0 = Normal operation
RXRST: Receive Logic Reset bit
1 = Receive logic is held in Reset
0 = Normal operation
DMAST: DMA Start and Busy Status bit
1 = DMA copy or checksum operation is in progress (set by software, cleared by hardware or software)
0 = DMA hardware is Idle
CSUMEN: DMA Checksum Enable bit
1 = DMA hardware calculates checksums
0 = DMA hardware copies buffer memory
TXRTS: Transmit Request to Send bit
1 = The transmit logic is attempting to transmit a packet (set by software, cleared by hardware or software)
0 = The transmit logic is Idle
RXEN: Receive Enable bit
1 = Packets which pass the current filter configuration will be written into the receive buffer
0 = All packets received will be discarded by hardware
Unimplemented: Read as ‘0’
RXRST
R/W-0
ECON1: ETHERNET CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
DMAST
R/W-0
CSUMEN
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F97J60 FAMILY
TXRTS
R/W-0
Many of the Ethernet SFRs in Bank 14 serve as pointer
registers to indicate addresses within the dedicated
Ethernet buffer for storage and retrieval of packet data.
Others store information for packet pattern masks or
checksum operations. Several are used for controlling
overall module operations, as well as specific MAC and
PHY functions.
18.2.3
The ECON1 register (Register 18-1) is used to control
the main functions of the module. Receive enable, trans-
mit request and DMA control bits are all located here.
The ECON2 register (Register 18-2) is used to control
other top level functions of the module. The ESTAT
register (Register 18-3) is used to report the high-level
status of the module and Ethernet communications.
The Ethernet SFRs with the ‘E’ prefix are always
accessible, regardless of whether or not the module is
enabled.
ETHERNET CONTROL REGISTERS
R/W-0
RXEN
x = Bit is unknown
U-0
—
DS39762C-page 213
U-0
—
bit 0