PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 468

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
Prescaler, Timer0 ............................................................. 165
Prescaler, Timer2 ............................................................. 187
PRI_IDLE Mode ................................................................. 50
PRI_RUN Mode ................................................................. 46
Program Counter ................................................................ 71
Program Memory
Program Memory Modes .................................................... 69
Program Verification and Code Protection ....................... 358
Programming, Device Instructions ................................... 359
PSP.See Parallel Slave Port.
Pulse-Width Modulation. See PWM (CCP Module)
PUSH ............................................................................... 388
PUSH and POP Instructions .............................................. 72
PUSHL ............................................................................. 404
PWM (CCP Module)
PWM (ECCP Module) ...................................................... 193
Q
Q Clock .................................................................... 187, 194
DS39762C-page 466
PCL, PCH and PCU Registers ................................... 71
PCLATH and PCLATU Registers .............................. 71
Extended Instruction Set ............................................ 90
Instructions ................................................................. 75
Interrupt Vector .......................................................... 68
Look-up Tables .......................................................... 73
Memory Maps ............................................................ 67
Memory Maps, Modes ............................................... 70
Modes
Reset Vector .............................................................. 68
Address Shifting (Extended Microcontroller) .............. 70
Extended Microcontroller ........................................... 69
Microcontroller ........................................................... 69
and PWM (ECCP Module).
Associated Registers ............................................... 188
Duty Cycle ................................................................ 186
Example Frequencies/Resolutions .......................... 187
Operation Setup ....................................................... 187
Period ....................................................................... 186
TMR2 to PR2 Match ................................................ 193
TMR4 to PR4 Match ................................................ 179
CCPR1H:CCPR1L Registers ................................... 193
Direction Change in Full-Bridge Output Mode ......... 198
Duty Cycle ................................................................ 194
Effects of a Reset ..................................................... 203
Enhanced PWM Auto-Shutdown ............................. 200
Example Frequencies/Resolutions .......................... 194
Full-Bridge Application Example .............................. 198
Full-Bridge Mode ...................................................... 197
Half-Bridge Mode ..................................................... 196
Half-Bridge Output Mode
Output Configurations .............................................. 194
Output Relationships (Active-High) .......................... 195
Output Relationships (Active-Low) ........................... 195
Period ....................................................................... 193
Programmable Dead-Band Delay ............................ 200
Setup for PWM Operation ........................................ 203
Start-up Considerations ........................................... 201
Two-Word .......................................................... 75
Hard Vectors and Configuration Words ............. 68
Memory Access (table) ...................................... 70
Applications Example ....................................... 196
Preliminary
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 51
RC_RUN Mode .................................................................. 48
RCALL ............................................................................. 389
RCON Register
Reader Response ............................................................ 472
Receive Filters
Register File Summary ................................................ 81–86
Registers
Bit Status During Initialization .................................... 58
AND Logic Flow ....................................................... 248
Magic Packet Format ............................................... 250
OR Logic Flow ......................................................... 247
Pattern Match Filter Format ..................................... 249
ADCON0 (A/D Control 0) ......................................... 325
ADCON1 (A/D Control 1) ......................................... 326
ADCON2 (A/D Control 2) ......................................... 327
BAUDCONx (Baud Rate Control x) ......................... 304
CCPxCON (Capture/Compare/PWM Control,
CCPxCON (Enhanced Capture/Compare/PWM
CMCON (Comparator Control) ................................ 335
CONFIG1H (Configuration 1 High) .......................... 347
CONFIG1L (Configuration 1 Low) ........................... 347
CONFIG2H (Configuration 2 High) .......................... 349
CONFIG2L (Configuration 2 Low) ........................... 348
CONFIG3H (Configuration 3 High) .......................... 351
CONFIG3L (Configuration 3 Low) ..................... 69, 350
CVRCON (Comparator Voltage
DEVID1 (Device ID 1) .............................................. 352
DEVID2 (Device ID 2) .............................................. 352
ECCPxAS (ECCPx Auto-Shutdown
ECCPxDEL (ECCPx Dead-Band Delay) ................. 200
ECON1 (Ethernet Control 1) .................................... 213
ECON2 (Ethernet Control 2) .................................... 214
EECON1 (EEPROM Control 1) ................................. 97
EFLOCON (Ethernet Flow Control) ......................... 244
EIE (Ethernet Interrupt Enable) ............................... 226
EIR (Ethernet Interrupt Request, Flag) .................... 227
ERXFCON (Ethernet Receive Filter Control) ........... 246
ESTAT (Ethernet Status) ......................................... 214
INTCON (Interrupt Control) ...................................... 121
INTCON2 (Interrupt Control 2) ................................. 122
INTCON3 (Interrupt Control 3) ................................. 123
IPR1 (Peripheral Interrupt Priority 1) ....................... 130
IPR2 (Peripheral Interrupt Priority 2) ....................... 131
IPR3 (Peripheral Interrupt Priority 3) ....................... 132
MABBIPG (MAC Back-to-Back
MACON1 (MAC Control 1) ...................................... 215
MACON3 (MAC Control 3) ...................................... 216
MACON4 (MAC Control 4) ...................................... 217
MEMCON (External Memory Bus Control) .............. 106
MICMD (MII Command) ........................................... 217
MISTAT (MII Status) ................................................ 218
OSCCON (Oscillator Control) .................................... 43
OSCTUNE (PLL Block Control) ................................. 41
CCP4 and CCP5) ............................................ 181
Control, ECCP1/ECCP2/ECCP3) .................... 189
Reference Control) .......................................... 341
Configuration) .................................................. 201
Inter-Packet Gap) ............................................ 232
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