PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 433

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 27-5:
TABLE 27-9:
© 2007 Microchip Technology Inc.
10
11
12
13
14
15
16
17
18
19
20
21
22†
23†
Param
No.
Note:
(Output)
I/O pin
(Input)
I/O pin
OSC1
CLKO
† These parameters are asynchronous events not related to any internal clock edges.
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OS
Symbol
OS
CK
CK
CK
CK
OS
OS
IO
IO
IO
IO
INP
RBP
V2
V2
R
F
H2
R
F
L2
H2
H2
H2
H2
Refer to Figure 27-3 for load conditions.
CK
OS
IO
CK
IO
CK
IO
IO
V CLKO ↓ to Port Out Valid
H Port In Valid before CLKO ↑
I
V OSC1 ↑ (Q1 cycle) to Port Out Valid
I
H Port Input Valid to OSC1 ↑
H OSC1 ↑ to CLKO ↑
L OSC1 ↑ to CLKO ↓
CLKO AND I/O TIMING REQUIREMENTS
CLKO Rise Time
CLKO Fall Time
Port In Hold after CLKO ↑
OSC1 ↑ (Q2 cycle) to Port Input Invalid
(I/O in hold time)
(I/O in setup time)
Port Output Rise Time
Port Output Fall Time
INTx pin High or Low Time
RB7:RB4 Change INTx High or Low Time
CLKO AND I/O TIMING
Old Value
Q4
Characteristic
10
13
17
14
20, 21
Q1
Preliminary
19
PIC18F97J60 FAMILY
0.25 T
18
Min
100
T
T
—
—
—
—
—
—
—
—
CY
0
0
CY
CY
+ 25
Q2
15
New Value
Typ
75
75
15
15
50
—
—
—
—
—
—
—
—
—
0.5 T
Max
200
200
150
CY
30
30
—
—
—
—
—
—
6
5
11
+ 20
12
16
DS39762C-page 431
Units Conditions
Q3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns