PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 335

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2007 Microchip Technology Inc.
21.7
The A/D converter in the PIC18F97J60 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for offset. Thus, subsequent offsets will
be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset, or if there are other major changes in
operating conditions.
21.8
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
TABLE 21-2:
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCP2CON
PORTA
TRISA
PORTF
TRISF
PORTH
TRISH
Legend:
Note 1:
Name
2:
(2)
(2)
A/D Converter Calibration
Operation in Power-Managed
Modes
Implemented in 100-pin devices only.
This register is not implemented on 64-pin devices.
— = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used for A/D conversion.
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register High Byte
A/D Result Register Low Byte
OSCFIF
OSCFIE
OSCFIP
TRISH7
TRISF7
ADCAL
PSPIF
PSPIE
PSPIP
ADFM
P2M1
RJPU
Bit 7
RH7
RF7
—
—
SUMMARY OF A/D REGISTERS
TRISH6
TRISF6
P2M0
CMIF
CMIE
CMIP
ADIE
ADIP
ADIF
Bit 6
RH6
RF6
—
—
—
—
—
TRISH5
TRISA5
TRISF5
VCFG1
ACQT2
DC2B1
RC1IF
RC1IE
RC1IP
ETHIF
ETHIE
ETHIP
CHS3
Bit 5
RA5
RH5
RF5
Preliminary
TRISH4
TRISA4
TRISF4
VCFG0
ACQT1
DC2B0
INT0IE
TX1IE
TX1IP
TX1IF
CHS3
Bit 4
RA4
RH4
RF4
r
r
r
PIC18F97J60 FAMILY
CCP2M3
TRISH3
SSP1IF
SSP1IE
SSP1IP
BCL1IE
BCL1IP
TRISA3
TRISF3
BCL1IF
PCFG3
ACQT0
CHS1
RBIE
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been
completed. If desired, the device may be placed into
the corresponding power-managed Idle mode during
the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits, ACQT2:ACQT0, are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
and SCS bits in the OSCCON register must have
already been cleared prior to starting the conversion.
Bit 3
RA3
RH3
RF3
CCP2M2
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISH2
TRISA2
TRISF2
PCFG2
ADCS2
CHS0
Bit 2
RA2
RH2
RF2
—
—
—
GO/DONE
CCP2M1
TMR2IE
TMR2IP
TMR3IE
TMR3IP
TMR2IF
TMR3IF
TRISA1
TRISH1
PCFG1
TRISF1
ADCS1
INT0IF
Bit 1
RH1
RA1
RF1
TRISF0
DS39762C-page 333
CCP2M0
TMR1IF
TMR1IE
TMR1IP
CCP2IE
CCP2IP
CCP2IF
TRISA0
TRISH0
PCFG0
ADCS0
ADON
RF0
RBIF
Bit 0
RH0
RA0
(1)
(1)
on Page:
Values
Reset
59
61
61
61
61
61
61
60
60
60
60
60
60
62
61
62
61
62
61