PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 471

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timing Diagrams and Specifications
© 2007 Microchip Technology Inc.
PWM Auto-Shutdown (P1RSEN = 0,
PWM Auto-Shutdown (P1RSEN = 1,
PWM Direction Change ........................................... 199
PWM Direction Change at Near
PWM Output ............................................................ 186
Repeated Start Condition ......................................... 289
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 318
Slave Synchronization ............................................. 261
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 260
SPI Mode (Slave Mode, CKE = 0) ........................... 262
SPI Mode (Slave Mode, CKE = 1) ........................... 262
Synchronous Reception (Master Mode, SREN) ...... 321
Synchronous Transmission ...................................... 319
Synchronous Transmission (Through TXEN) .......... 320
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 435
Transition for Entry to Idle Mode ................................ 50
Transition for Entry to SEC_RUN Mode .................... 47
Transition for Entry to Sleep Mode ............................ 49
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode .............. 50
Transition for Wake From Sleep Mode (HSPLL) ....... 49
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 48
AC Characteristics
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ........................... 431, 432
EUSARTx Synchronous Receive Requirements ..... 445
EUSARTx Synchronous Transmission
Example SPI Mode Requirements
Auto-Restart Disabled) .................................... 202
Auto-Restart Enabled) ..................................... 202
100% Duty Cycle ............................................. 199
Timer (OST) and Power-up Timer (PWRT) ..... 434
V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTRC to HSPLL) ........................................... 355
PRI_RUN Mode ................................................. 48
PRI_RUN Mode (HSPLL) .................................. 47
Internal RC Accuracy ....................................... 430
(Including ECCPx Modules) ............................. 436
Requirements .................................................. 445
DD
Rise > T
PWRT
DD
) ............................................ 57
, V
DD
DD
DD
), Case 1 ....................... 56
), Case 2 ....................... 57
Rise < T
DD
,
PWRT
) ........... 56
Preliminary
PIC18F97J60 FAMILY
Top-of-Stack Access .......................................................... 71
TRISE Register
TSTFSZ ........................................................................... 399
Two-Speed Start-up ................................................. 345, 355
Two-Word Instructions
TXSTAx Register
V
V
Voltage Reference Specifications .................................... 426
Voltage Regulator (On-Chip) ........................................... 354
W
Watchdog Timer (WDT) ........................................... 345, 353
WCOL ...................................................... 288, 289, 290, 293
WCOL Status Flag ................................... 288, 289, 290, 293
WWW Address ................................................................ 471
WWW, On-Line Support ...................................................... 6
X
XORLW ........................................................................... 399
XORWF ........................................................................... 400
DDCORE
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 429
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements ............................ 436
PLL Clock ................................................................ 430
Program Memory Write Requirements .................... 433
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
PSPMODE Bit ......................................................... 159
Example Cases ......................................................... 75
BRGH Bit ................................................................. 305
Associated Registers ............................................... 353
Control Register ....................................................... 353
Programming Considerations .................................. 353
2
2
C Bus Data Requirements (Slave Mode) .............. 442
C Bus Start/Stop Bits Requirements
/V
(Master Mode, CKE = 0) .................................. 437
(Master Mode, CKE = 1) .................................. 438
(Slave Mode, CKE = 0) .................................... 439
(CKE = 1) ......................................................... 440
(Slave Mode) ................................................... 441
Requirements .................................................. 443
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 434
Requirements .................................................. 435
CAP
Pin .......................................................... 354
2
2
C Bus Data Requirements ................ 444
C Bus Start/Stop Bits
DS39762C-page 469