PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 470

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
Timer0 .............................................................................. 163
Timer1 .............................................................................. 167
Timer2 .............................................................................. 173
Timer3 .............................................................................. 175
Timer4 .............................................................................. 179
Timing Diagrams
DS39762C-page 468
Associated Registers ............................................... 165
Clock Source Select (T0CS Bit) ............................... 164
Operation ................................................................. 164
Overflow Interrupt .................................................... 165
Prescaler .................................................................. 165
Prescaler Assignment (PSA Bit) .............................. 165
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 165
Prescaler, Switching Assignment ............................. 165
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 164
Source Edge Select (T0SE Bit) ................................ 164
16-Bit Read/Write Mode ........................................... 169
Associated Registers ............................................... 171
Considerations in Asynchronous Counter Mode ...... 170
Interrupt .................................................................... 170
Operation ................................................................. 168
Oscillator .......................................................... 167, 169
Overflow Interrupt .................................................... 167
Resetting, Using the ECCPx
Special Event Trigger (ECCP) ................................. 192
TMR1H Register ...................................................... 167
TMR1L Register ....................................................... 167
Use as a Clock Source ............................................ 169
Use as a Real-Time Clock ....................................... 170
Associated Registers ............................................... 174
Interrupt .................................................................... 174
Operation ................................................................. 173
Output ...................................................................... 174
PR2 Register .................................................... 186, 193
TMR2 to PR2 Match Interrupt .................................. 193
16-Bit Read/Write Mode ........................................... 177
Associated Registers ............................................... 177
Operation ................................................................. 176
Oscillator .......................................................... 175, 177
Overflow Interrupt ............................................ 175, 177
Resetting Using the ECCPx
TMR3H Register ...................................................... 175
TMR3L Register ....................................................... 175
Associated Registers ............................................... 180
MSSPx Clock, Output .............................................. 180
Operation ................................................................. 179
Postscaler. See Postscaler, Timer4.
PR4 Register .................................................... 179, 186
Prescaler. See Prescaler, Timer4.
TMR4 Register ......................................................... 179
TMR4 to PR4 Match Interrupt .......................... 179, 180
A/D Conversion ........................................................ 446
Asynchronous Reception, RXDTP = 0
Asynchronous Transmission (Back-to-Back),
Asynchronous Transmission, TXCKP = 0
Automatic Baud Rate Calculation ............................ 310
Auto-Wake-up Bit (WUE) During
Layout Considerations ..................................... 169
Special Event Trigger ....................................... 170
Special Event Trigger ....................................... 177
(RXx Not Inverted) ........................................... 315
TXCKP = 0 (TXx Not Inverted) ........................ 312
(TXx Not Inverted) ............................................ 312
Normal Operation ............................................. 317
Preliminary
Auto-Wake-up Bit (WUE) During Sleep ................... 317
Baud Rate Generator with Clock Arbitration ............ 287
BRG Overflow Sequence ......................................... 310
BRG Reset Due to SDAx Arbitration During
Capture/Compare/PWM (Including
CLKO and I/O .......................................................... 431
Clock Synchronization ............................................. 280
Clock/Instruction Cycle .............................................. 74
EUSARTx Synchronous Receive
EUSARTx Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 437
Example SPI Master Mode (CKE = 1) ..................... 438
Example SPI Slave Mode (CKE = 0) ....................... 439
Example SPI Slave Mode (CKE = 1) ....................... 440
External Clock (All Modes Except PLL) ................... 429
External Memory Bus for Sleep (Extended
External Memory Bus for TBLRD (Extended
Fail-Safe Clock Monitor ........................................... 357
First Start Bit ............................................................ 288
Full-Bridge PWM Output .......................................... 197
Half-Bridge PWM Output ......................................... 196
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I
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I
I
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I
I
I
I
I
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I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ............................... 161
Parallel Slave Port (PSP) Write ............................... 160
Program Memory Read ........................................... 432
Program Memory Write ............................................ 433
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Acknowledge Sequence .................................... 293
C Bus Collision During a Repeated Start
C Bus Collision During a Repeated Start
C Bus Collision During a Stop
C Bus Collision During a Stop
C Bus Collision During Start
C Bus Collision During Start
C Bus Collision for Transmit and
C Bus Data ............................................................ 441
C Bus Start/Stop Bits ............................................ 441
C Master Mode (7 or 10-Bit Transmission) ........... 291
C Master Mode (7-Bit Reception) .......................... 292
C Slave Mode (10-Bit Reception, SEN = 0) .......... 276
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 1) .......... 282
C Slave Mode (10-Bit Transmission) .................... 278
C Slave Mode (7-Bit Reception, SEN = 0) ............ 273
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 1) ............ 281
C Slave Mode (7-Bit Transmission) ...................... 275
C Slave Mode General Call Address Sequence
C Stop Condition Receive or Transmit Mode ........ 293
Start Condition ................................................. 296
ECCPx Modules) ............................................. 436
(Master/Slave) ................................................. 445
(Master/Slave) ................................................. 445
Microcontroller Mode) .............................. 112, 114
Microcontroller Mode) .............................. 112, 114
Condition (Case 1) ........................................... 297
Condition (Case 2) ........................................... 297
Condition (Case 1) ........................................... 298
Condition (Case 2) ........................................... 298
Condition (SCLx = 0) ....................................... 296
Condition (SDAx Only) .................................... 295
Acknowledge ................................................... 294
ADMSK = 01001) ............................................ 277
ADMSK = 01011) ............................................ 274
(7 or 10-Bit Addressing Mode) ......................... 283
2
2
C Bus Data ........................................ 443
C Bus Start/Stop Bits ........................ 443
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