PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 464

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
Extended Instruction Set
External Clock Input (EC Modes) ....................................... 40
External Memory Bus ....................................................... 105
F
Fail-Safe Clock Monitor ............................................ 345, 356
Fast Register Stack ............................................................ 73
Firmware Instructions ....................................................... 359
Flash Configuration Words ......................................... 68, 345
Flash Program Memory ...................................................... 95
DS39762C-page 462
Synchronous Master Mode ...................................... 319
Synchronous Slave Mode ........................................ 322
ADDFSR .................................................................. 402
ADDULNK ................................................................ 402
CALLW ..................................................................... 403
MOVSF .................................................................... 403
MOVSS .................................................................... 404
PUSHL ..................................................................... 404
SUBFSR .................................................................. 405
SUBULNK ................................................................ 405
16-Bit Byte Select Mode .......................................... 111
16-Bit Byte Write Mode ............................................ 109
16-Bit Data Width Modes ......................................... 108
16-Bit Mode Timing .................................................. 112
16-Bit Word Write Mode ........................................... 110
21-Bit Addressing ..................................................... 107
8-Bit Data Width Mode ............................................. 113
8-Bit Mode Timing .................................................... 114
Address and Data Line Usage (table) ...................... 107
Address and Data Width .......................................... 107
Address Shifting ....................................................... 107
Control ..................................................................... 106
I/O Port Functions .................................................... 105
Operation in Power-Managed Modes ...................... 115
Program Memory Modes ......................................... 108
Wait States ............................................................... 108
Weak Pull-ups on Port Pins ..................................... 108
and the Watchdog Timer .......................................... 356
Exiting Operation ..................................................... 356
Interrupts in Power-Managed Modes ....................... 357
POR or Wake-up From Sleep .................................. 357
Associated Registers ............................................... 103
Control Registers ....................................................... 96
Erase Sequence ...................................................... 100
Erasing ..................................................................... 100
Operation During Code-Protect ............................... 103
Reading ...................................................................... 99
Table Pointer
Table Pointer Boundaries .......................................... 98
Table Reads and Table Writes .................................. 95
Write Sequence ....................................................... 101
Associated Registers, Receive ........................ 322
Associated Registers, Transmit ....................... 320
Reception ......................................................... 321
Transmission .................................................... 319
Associated Registers, Receive ........................ 324
Associated Registers, Transmit ....................... 323
Reception ......................................................... 323
Transmission .................................................... 322
Extended Microcontroller ................................. 108
Microcontroller ................................................. 108
EECON1 and EECON2 ..................................... 96
TABLAT (Table Latch) Register ......................... 98
TBLPTR (Table Pointer) Register ...................... 98
Boundaries Based on Operation ........................ 98
Preliminary
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 380
H
Hardware Multiplier .......................................................... 117
I
I/O Ports ........................................................................... 135
I
INCF ................................................................................ 380
INCFSZ ............................................................................ 381
In-Circuit Debugger .......................................................... 358
In-Circuit Serial Programming (ICSP) ...................... 345, 358
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ................................. 91, 93, 406
Indirect Addressing ............................................................ 89
2
C Mode (MSSP) ............................................................ 265
Writing ..................................................................... 101
Introduction .............................................................. 117
Operation ................................................................. 117
Performance Comparison ........................................ 117
Pin Capabilities ........................................................ 135
Acknowledge Sequence Timing .............................. 293
Associated Registers ............................................... 299
Baud Rate Generator .............................................. 286
Bus Collision
Clock Arbitration ...................................................... 287
Clock Rate w/BRG ................................................... 286
Clock Stretching ....................................................... 279
Clock Synchronization and the CKP Bit ................... 280
Effects of a Reset .................................................... 294
General Call Address Support ................................. 283
Master Mode ............................................................ 284
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 294
Operation ................................................................. 270
Read/Write Bit Information (R/W Bit) ............... 270, 272
Registers ................................................................. 265
Serial Clock (SCKx/SCLx) ....................................... 272
Slave Mode .............................................................. 270
Sleep Operation ....................................................... 294
Stop Condition Timing ............................................. 293
and Standard PIC18 Instructions ............................. 406
BSR ........................................................................... 93
Protection Against Spurious Writes ................. 103
Unexpected Termination ................................. 103
Write Verify ...................................................... 103
During a Repeated Start Condition .................. 297
During a Stop Condition .................................. 298
10-Bit Slave Receive Mode (SEN = 1) ............ 279
10-Bit Slave Transmit Mode ............................ 279
7-Bit Slave Receive Mode (SEN = 1) .............. 279
7-Bit Slave Transmit Mode .............................. 279
Baud Rate Generator ...................................... 286
Operation ......................................................... 285
Reception ........................................................ 290
Repeated Start Condition Timing .................... 289
Start Condition Timing ..................................... 288
Transmission ................................................... 290
and Arbitration ................................................. 294
Address Masking ............................................. 271
Addressing ....................................................... 270
Reception ........................................................ 272
Transmission ................................................... 272
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