PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 88

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
TABLE 5-5:
DS39762C-page 86
EHT7
EHT6
EHT5
EHT4
EHT3
EHT2
EHT1
EHT0
MIRDH
MIRDL
MIWRH
MIWRL
MIREGADR
MICMD
MAMXFLH
MAMXFLL
MAIPGH
MAIPGL
MABBIPG
MACON4
MACON3
MACON1
EPAUSH
EPAUSL
EFLOCON
MISTAT
MAADR2
MAADR1
MAADR4
MAADR3
MAADR6
MAADR5
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition, r = reserved bit, do not modify. Shaded cells
Note 1:
File Name
2:
3:
4:
5:
6:
7:
8:
9:
are unimplemented, read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
Bit 21 of the PC is only available in Serial Programming modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
Alternate names and definitions for these bits when the MSSP module is operating in I
These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
These bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
Implemented in 100-pin devices in Microcontroller mode only.
Hash Table Register Byte 7
Hash Table Register Byte 6
Hash Table Register Byte 5
Hash Table Register Byte 4
Hash Table Register Byte 3
Hash Table Register Byte 2
Hash Table Register Byte 1
Hash Table Register Byte 0
MII Read Data Register High Byte
MII Read Data Register Low Byte
MII Write Data Register High Byte
MII Write Data Register Low Byte
Maximum Frame Length Register High Byte
Maximum Frame Length Register Low Byte
Pause Timer Value Register High Byte
Pause Timer Value Register Low Byte
MAC Address Register Byte 2 (MAADR<39:32>), OUI Byte 2
MAC Address Register Byte 1 (MAADR<47:40>), OUI Byte 1
MAC Address Register Byte 4 (MAADR<23:16>)
MAC Address Register Byte 3 (MAADR<31:24>), OUI Byte 3
MAC Address Register Byte 6 (MAADR<7:0>)
MAC Address Register Byte 5 (MAADR<15:8>)
PADCFG2
Bit 7
—
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
MAC Non Back-to-Back Inter-Packet Gap Register High Byte
MAC Non Back-to-Back Inter-Packet Gap Register Low Byte
PADCFG1
BBIPG6
DEFER
Bit 6
—
—
—
—
—
PADCFG0
BBIPG5
Bit 5
—
—
—
—
—
r
MII Address Register
TXCRCEN
BBIPG4
Bit 4
—
—
—
r
r
Preliminary
PHDREN
TXPAUS
BBIPG3
Bit 3
—
—
—
r
HFRMEN
RXPAUS
BBIPG2
NVALID
Bit 2
—
—
r
2
C™ Slave mode.
FRMLNEN
PASSALL
MIISCAN
BBIPG1
FCEN1
SCAN
Bit 1
r
© 2007 Microchip Technology Inc.
MARXEN
FULDPX
BBIPG0
FCEN0
MIIRD
BUSY
Bit 0
r
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
---0 0000
---- --00
0000 0110
0000 0000
-000 0000
-000 0000
-000 0000
-000 --00
0000 0000
---0 0000
0001 0000
0000 0000
---- -000
---- 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
POR, BOR
Values on
Details on
64, 245
64, 245
64, 245
64, 245
64, 245
64, 245
64, 245
64, 245
64, 218
64, 218
64, 218
64, 218
64, 218
64, 217
64, 231
64, 231
65, 231
65, 231
65, 232
65, 217
65, 216
65, 215
65, 244
65, 244
65, 244
65, 218
65, 231
65, 231
65, 231
65, 231
65, 231
65, 231
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