MC908QB8CDWE Freescale Semiconductor, MC908QB8CDWE Datasheet - Page 126

IC MCU 8BIT 8K FLASH 16-SOIC

MC908QB8CDWE

Manufacturer Part Number
MC908QB8CDWE
Description
IC MCU 8BIT 8K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QB8CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
14
Number Of Timers
4
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
DEMO908QB8 - BOARD DEMO FOR MC68HC908QB8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Enhanced Serial Communications Interface (ESCI) Module
ORIE — Receiver Overrun Interrupt Enable Bit
NEIE — Receiver Noise Error Interrupt Enable Bit
FEIE — Receiver Framing Error Interrupt Enable Bit
PEIE — Receiver Parity Error Interrupt Enable Bit
13.8.4 ESCI Status Register 1
ESCI status register 1 (SCS1) contains flags to signal these conditions:
SCTE — ESCI Transmitter Empty Bit
126
This read/write bit enables ESCI error interrupt requests generated by the receiver overrun bit, OR.
This read/write bit enables ESCI error interrupt requests generated by the noise error bit, NE.
This read/write bit enables ESCI error interrupt requests generated by the framing error bit, FE.
This read/write bit enables ESCI receiver interrupt requests generated by the parity error bit, PE.
This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register.
SCTE can generate an ESCI transmitter interrupt request. When the SCTIE bit in SCC2 is set, SCTE
generates an ESCI transmitter interrupt request. In normal operation, clear the SCTE bit by reading
SCS1 with SCTE set and then writing to SCDR
1 = ESCI error interrupt requests from OR bit enabled
0 = ESCI error interrupt requests from OR bit disabled
1 = ESCI error interrupt requests from NE bit enabled
0 = ESCI error interrupt requests from NE bit disabled
1 = ESCI error interrupt requests from FE bit enabled
0 = ESCI error interrupt requests from FE bit disabled
1 = ESCI error interrupt requests from PE bit enabled
0 = ESCI error interrupt requests from PE bit disabled
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
Reset:
Read:
Write:
SCTE
Bit 7
1
Figure 13-12. ESCI Status Register 1 (SCS1)
= Unimplemented
TC
6
1
MC68HC908QB8 Data Sheet, Rev. 3
SCRF
5
0
IDLE
0
4
OR
3
0
NF
2
0
FE
1
0
Freescale Semiconductor
Bit 0
PE
0

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