DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet
DF2117VLP20V
Specifications of DF2117VLP20V
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DF2117VLP20V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2117 Group 16 Hardware Manual Renesas 16-Bit ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Rev. 3.00 Sep. 28, 2009 Page iv of xliv REJ09B0350-0300 ...
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Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users ...
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Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this ...
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Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described ...
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Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG Clock pulse generator INT Interrupt controller SCI Serial communication interface TMR 8-bit timer TPU 16-bit ...
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Main Revisions for This Edition Item 1.3 Block Diagram Figure 1.2 Internal Block Diagram 2.4.3 Extended Control Register (EXR) 2.4.4 Condition-Code Register (CCR) 6.1 Register Descriptions Table 6.1 Register Configuration 6.1.2 Wait State Control Register (WSCR) 7.2.16 Port G (5) ...
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Item 7.2.19 Port J Table 7.4 Available Output Signals and Settings in Each Port 8.2 Input/Output Pins Table 8.1 Pin Configuration Rev. 3.00 Sep. 28, 2009 Page x of xliv REJ09B0350-0300 Page Revision (See Manual for Details) 188 Table amended ...
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Item 8.4.2 Pulse Division Mode Figure 8.8 Example of Additional Pulse Timing (Upper 4 Bits in PWMREG = B'1000) Figure 8.9 Example of WMU Setting 10.3.3 Timer I/O Control Register (TIOR) Table 10.13 TIORL_0 (channel 0) 11.3.6 TCM Status Register ...
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Item 15.1 Features Figure 15.1 Block Diagram of SCI 15.3 Register Descriptions Table 15.2 Register Configuration 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.9 Sample Serial Reception Flowchart (1) Rev. 3.00 Sep. 28, 2009 Page xii of xliv REJ09B0350-0300 Page ...
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Item 15.5.1 Multiprocessor Serial Data Transmission Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.17 Sample Serial Transmission Flowchart 15.6.4 ...
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Item 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception 16.3.8 FIFO Control Register (FFCR) 16.4.4 Data Transmission/ Reception with Flow Control Figure 16.6 Example of Initialization Flowchart Figure ...
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Item 17.4.5 Slave Receive Operation Figure 17.15 Example of Slave Receive Mode Operation Timing (2) (MLS = 0) 18.3 Register Descriptions Table 18.2 Register Configuration 18.3.2 Keyboard Buffer Control Register 2 (KBCR2) 18.3.6 Keyboard Buffer Transmit Data Register (KBTR) 18.4.8 ...
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Item 18.5.4 Medium-Speed Mode 19.3 Register Descriptions Table 19.2 Register Configuration 19.3.11 Bidirectional Data Registers (TWR0 to TWR15) 19.3.12 Status Registers (STR1 to STR4) • STR4 Rev. 3.00 Sep. 28, 2009 Page xvi of ...
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Item 19.4.4 LPC Interface Shutdown Function (LPCPD) Table 19.7 Scope of Initialization in Each LPC interface Mode 19.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) Table 19.8 Serialized Interrupt Transfer Cycle Frame Configuration 20.3 Register Descriptions Table 20.2 Register Configuration 20.7.2 ...
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Item 20.7.6 Notes on Noise Countermeasures Figure 20.7 Analog Input Pin Equivalent Circuit 22.1 Features 22.2 Mode Transition Diagram Table 22.1 Differences between Boot Mode, User Program Mode, and Programmer Mode Rev. 3.00 Sep. 28, 2009 Page xviii of xliv ...
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Item 22.2 Mode Transition Diagram 22.5 Programming/Erasing Interface 22.7.1 Programming/Erasing Interface Registers (5) Flash MAT Select Register (FMATS) Page Revision (See Manual for Details) 678 Description added • The user boot Mat can be programmed or erased only in boot ...
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Item 22.7.1 Programming/Erasing Interface Registers (5) Flash MAT Select Register (FMATS) 22.8.2 User Program Mode (3) Erasing Procedure in User Program Mode Rev. 3.00 Sep. 28, 2009 Page xx of xliv REJ09B0350-0300 Page Revision (See Manual for Details) 689 Note ...
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Item 22.8.4 Storable Areas for On- Chip Program and Program Data Table 22.9 Executable Memory MAT Page Revision (See Manual for Details) 719 Description amended • operating mode in which the external address space is not accessible, such ...
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Item 22.8.4 Storable Areas for On- Chip Program and Program Data Table 22.10 Usable Area for Programming in User Program Mode Table 22.11 Usable Area for Erasure in User Program Mode Table 22.12 Usable Area for Programming in User Boot ...
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Item 22.12 Standard Serial Communication Interface Specifications for Boot Mode Figure 22.18 Boot Program States Table 22.17 Inquiry and Selection Commands (3) Inquiry and Selection States (f) Operating Clock Frequency Inquiry (8) Programming/Erasing State (c) 128-Byte Programming Page Revision (See ...
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Item 22.12 Standard Serial Communication Interface Specifications for Boot Mode (8) Programming/Erasing State (f) Memory Read 22.13 Usage Notes 25.1 Register Addresses (Address Order) Rev. 3.00 Sep. 28, 2009 Page xxiv of xliv REJ09B0350-0300 Page Revision (See Manual for Details) ...
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Item 25.2 Register Bits 25.3 Register States in Each Operating Mode 25.4 Register Selection Condition Page Revision (See Manual for Details) 807 Table amended Register Abbreviation Bit 7 Bit 6 Bit 5 ADDRA Bit 15 Bit 14 Bit 13 Bit ...
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Item 25.5 Register Addresses (Classification by Type of Module) 26.3.2 Control Signal Timing Figure 26.8 Interrupt Input Timing 26.3.3 Timing of On-Chip Peripheral Modules Table 26.8 PS2 Timing 2 Table 26 Bus Timing Table 26.10 LPC Timing Rev. ...
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Item 26.3.3 Timing of On-Chip Peripheral Modules Table 26.11 JTAG Timing 26.6 Usage Notes Page Revision (See Manual for Details) 894 Table amended Test Conditions Figure 26.26 Figure 26.27 Figure 26.28 898 Description amended … An example of connection is ...
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All trademarks and registered trademarks are the property of their respective owners. Rev. 3.00 Sep. 28, 2009 Page xxviii of xliv REJ09B0350-0300 ...
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Section 1 Overview..............................................................................................1 1.1 Features.................................................................................................................................. 1 1.1.1 Applications .............................................................................................................. 1 1.1.2 Overview of Functions.............................................................................................. 2 1.2 List of Products ...................................................................................................................... 7 1.3 Block Diagram ....................................................................................................................... 8 1.4 Pin Descriptions ..................................................................................................................... 9 1.4.1 Pin Assignments ....................................................................................................... 9 1.4.2 Pin Assignment in ...
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Register Indirect with Displacement⎯@(d:16, ERn) or @(d:32, ERn)................. 58 2.7.4 Register Indirect with Post-Increment or Pre-Decrement⎯@ERn+ or @-ERn..... 58 2.7.5 Absolute Address⎯@aa:8, @aa:16, @aa:24, or @aa:32....................................... 58 2.7.6 Immediate⎯#xx:8, #xx:16, or #xx:32.................................................................... 59 2.7.7 Program-Counter Relative⎯@(d:8, PC) or @(d:16, ...
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Address Break Control Register (ABRKCR) ......................................................... 91 5.3.3 Break Address Registers (BARA to BARC) ............................................... 92 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) ................... 93 5.3.5 IRQ Enable Registers (IER16, IER) ....................................................................... 96 5.3.6 ...
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Section 7 I/O Ports...........................................................................................135 7.1 Register Descriptions ......................................................................................................... 143 7.1.1 Data Direction Register (PnDDR and ............... 144 7.1.2 Data Register (PnDR ...
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Section 8 8-Bit PWM Timer (PWMU)............................................................197 8.1 Features.............................................................................................................................. 197 8.2 Input/Output Pins ............................................................................................................... 199 8.3 Register Descriptions ......................................................................................................... 200 8.3.1 PWM Control Register A (PWMCONA) ............................................................. 202 8.3.2 PWM Control Register B (PWMCONB).............................................................. 202 8.3.3 PWM Control Register C (PWMCONC).............................................................. ...
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Timer Counter (TCNT)......................................................................................... 263 10.3.7 Timer General Register (TGR) ............................................................................. 263 10.3.8 Timer Start Register (TSTR) ................................................................................ 263 10.3.9 Timer Synchro Register (TSYR) .......................................................................... 264 10.4 Interface to Bus Master...................................................................................................... 265 10.4.1 16-Bit Registers .................................................................................................... 265 10.4.2 8-Bit Registers ...
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TCM Cycle Lower Limit Register (TCMMINCM) .............................................. 310 11.3.4 TCM Input Capture Register (TCMICR).............................................................. 310 11.3.5 TCM Input Capture Buffer Register (TCMICRF) ................................................ 310 11.3.6 TCM Status Register (TCMCSR) ......................................................................... 311 11.3.7 TCM Control Register (TCMCR)......................................................................... 313 11.3.8 TCM ...
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Usage Notes ....................................................................................................................... 352 12.6.1 Conflict between TDPCNT Write and Count-Up Operation ................................ 352 12.6.2 Conflict between TDPPDMX Write and Compare Match.................................... 352 12.6.3 Conflict between Input Capture and TDPICR Read ............................................. 353 12.6.4 Conflict between Edge Detection in ...
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Input Capture Operation ....................................................................................... 381 13.8 Interrupt Sources................................................................................................................ 383 13.9 Usage Notes ....................................................................................................................... 384 13.9.1 Conflict between TCNT Write and Counter Clear................................................ 384 13.9.2 Conflict between TCNT Write and Count-Up ...................................................... 384 13.9.3 Conflict between TCOR Write and Compare-Match............................................ ...
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Bit Rate Register (BRR) ....................................................................................... 418 15.4 Operation in Asynchronous Mode ..................................................................................... 423 15.4.1 Data Transfer Format............................................................................................ 424 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode............................................................................................. 425 15.4.3 Clock..................................................................................................................... 426 15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 427 ...
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Note on Writing to Registers in Transmission, Reception, and Simultaneous Transmission and Reception .......................................................... 466 Section 16 Serial Communication Interface with FIFO (SCIF) ........................467 16.1 Features.............................................................................................................................. 467 16.2 Input/Output Pins ............................................................................................................... 469 16.3 Register Descriptions ......................................................................................................... 470 16.3.1 Receive ...
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I C Bus Control Register (ICCR).......................................................................... 516 2 17.3 Bus Status Register (ICSR)............................................................................. 525 2 17.3 Bus Control Initialization Register (ICRES)................................................... 529 2 17.3 Bus Extended Control Register (ICXR).......................................................... 530 17.4 Operation ...
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Usage Notes ....................................................................................................................... 587 18.5.1 KBIOE Setting and KCLK Falling Edge Detection.............................................. 587 18.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission .................... 588 18.5.3 Module Stop Mode Setting ................................................................................... 588 18.5.4 Medium-Speed Mode............................................................................................ 588 18.5.5 Transmit ...
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SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15............................ 648 19.6 Usage Note......................................................................................................................... 652 19.6.1 Data Conflict......................................................................................................... 652 Section 20 A/D Converter .................................................................................655 20.1 Features.............................................................................................................................. 655 20.2 Input/Output Pins............................................................................................................... 657 20.3 Register ...
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Boot Mode ............................................................................................................ 702 22.8.2 User Program Mode.............................................................................................. 706 22.8.3 User Boot Mode.................................................................................................... 715 22.8.4 Storable Areas for On-Chip Program and Program Data...................................... 719 22.9 Protection ........................................................................................................................... 724 22.9.1 Hardware Protection ............................................................................................. 724 22.9.2 Software Protection............................................................................................... 725 22.9.3 Error ...
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Section 25 List of Registers...............................................................................781 25.1 Register Addresses (Address Order).................................................................................. 782 25.2 Register Bits....................................................................................................................... 803 25.3 Register States in Each Operating Mode ........................................................................... 820 25.4 Register Selection Condition ............................................................................................. 834 25.5 Register Addresses (Classification by Type of Module).................................................... 854 Section ...
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Features The core of each product in the H8S/2117 Group of CISC (complex instruction set computer) microcomputers is an H8S/2600 CPU, which has an internal 16-bit architecture. The H8S/2600 CPU provides upward-compatibility with the CPUs of other Renesas Technology-original ...
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Section 1 Overview 1.1.2 Overview of Functions Table 1.1 lists the functions of this LSI in outline. Table 1.1 Overview of Functions Module/ Classification Function Memory ROM RAM CPU CPU Operating mode Rev. 3.00 Sep. 28, 2009 Page 2 of ...
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Module/ Classification Function CPU MCU operating mode Interrupt Interrupt (source) controller Clock Clock pulse generator (CPG) A/D converter A/D converter (ADC) Description Mode 2: Single-chip mode (selected by driving the MD2 and MD0 pins low and MD1 pin high) Mode ...
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Section 1 Overview Module/ Classification Function Timer 8-bit PWM timer (PWMU) 14-bit PWM timer (PWMX) 16-bit timer pulse unit (TPU) 16-bit cycle measurem- ent timer (TCM) 16-bit duty period measurem- ent timer (TDP) Rev. 3.00 Sep. 28, 2009 Page 4 ...
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Module/ Classification Function Timer 8-bit timer (TMR) Watchdog timer Watchdog timer (WDT) Serial interface Serial communic- ation interface with FIFO (SCIF) Serial communi- cation interface (SCI) Smart card/ SIM 2 High bus performance interface communication (IIC) Keyboard buffer ...
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Section 1 Overview Module/ Classification Function I/O ports Package Operating frequency/ Power supply voltage Operating peripheral temperature (°C) Rev. 3.00 Sep. 28, 2009 Page 6 of 910 REJ09B0350-0300 Description • Input-only pins: 13 pins • Input/output pins: 112 pins (TFP-144V ...
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List of Products Table 1.2 is the list of products, and figure 1.1 shows how to read the product name code. Table 1.2 List of Products Part No. ROM Capacity R4F2117 160 Kbytes Part no Figure ...
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Section 1 Overview 1.3 Block Diagram VCC VCC VCC VCL VSS VSS VSS VSS VSS RES XTAL EXTAL MD2 MD1 NMI ETRST 2 PJ0* 2 PJ1* 2 PJ2* 2 PJ3* 2 PJ4* 2 PJ5* 2 PJ6* 2 PJ7* 2 PI0* ...
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Pin Descriptions 1.4.1 Pin Assignments 108 107 106 105 109 P12 110 P11 VSS 111 112 P10 113 PB7/RTS PB6/CTS 114 115 PB5/DTR PB4/DSR 116 117 PB3/DCD/PWMU1B 118 PB2/RI/PWMU0B 119 PB1/LSCI 120 PB0/LSMI P30/LAD0 121 P31/LAD1 122 123 P32/LAD2 ...
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Section 1 Overview 15 P12 P14 P17 14 PJ4 P13 P15 13 VSS VSS P11 12 PB6 P10 PJ3 11 PB3 PB4 PB5 10 PB1 PB0 PJ2 9 P32 P33 P31 8 P36 PJ1 P35 7 P81 P82 P80 6 ...
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P11 P13 P15 P20 13 P12 P10 P16 P22 12 PB7 VSS PB6 P14 11 PB3 PB5 PB4 P17 10 P30 PB2 PB1 P31 9 P34 PB0 P32 P35 8 P80 P33 P82 P36 7 P84 P81 P86 P37 6 ...
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Section 1 Overview 1.4.2 Pin Assignment in Each Operating Mode Table 1.3 H8S/2117 Group Pin Assignment in Each Operating Mode Pin No. Single-Chip Mode TFP- BP- TLP- 144V 176V 145V Mode 2 (EXPE = VCC 2 ...
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Pin No. Single-Chip Mode TFP- BP- TLP- 144V 176V 145V Mode 2 (EXPE = P92/IRQ0 P91/IRQ1 P90/IRQ2 ⎯ ⎯ K3 (N) PI4 MD2 PH2 ...
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Section 1 Overview Pin No. Single-Chip Mode TFP- BP- TLP- 144V 176V 145V Mode 2 (EXPE = PF5/PWMU3A PF4/PWMU2A PF3/IRQ11/TMOX/TDPCKI0/TDPMCI0 PF2/IRQ10/TMOY/TDPCYI0 PF1/IRQ9/PWMU1A 50 M7 ...
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Pin No. Single-Chip Mode TFP- BP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) ⎯ ⎯ M12 NC 70 P13 L10 P72/AN2 71 R14 N11 P73/AN3 72 P14 N12 P74/AN4 73 R15 M13 P75/AN5 74 N13 N13 P76/AN6 75 ...
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Section 1 Overview Pin No. Single-Chip Mode TFP- BP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) 92 G13 F12 PC2/TIOCC0/TCLKA/WUE10 93 G15 G13 PC1/TIOCB0/WUE9 94 G14 G11 PC0/TIOCA0/WUE8 95 F12 F10 VSS ⎯ ⎯ F13 VSS ⎯ ⎯ ...
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Pin No. Single-Chip Mode TFP- BP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) 116 B11 C10 PB4/DSR 117 A11 A10 PB3/DCD/PWMU1B 118 D10 B9 PB2/RI/PWMU0B ⎯ ⎯ C10 PJ2 119 A10 C9 PB1/LSCI 120 B10 B8 PB0/LSMI 121 ...
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Section 1 Overview Pin No. Single-Chip Mode TFP- BP- TLP- 144V 176V 145V Mode 2 (EXPE = 0) ⎯ ⎯ 141 D4 B3 PH4 142 B3 C4 PH5 143 A2 A3 XTAL 144 B2 A2 EXTAL Notes: (N) ...
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Pin Functions Table 1.4 Pin Functions Type Symbol TFP-144V BP-176V TLP-145V I/O Power VCC 1, 36, 86 supply VCL 13 VSS 7, 42, 95, 111, 139 Clock XTAL 143 EXTAL 144 φ 18 EXCL 18 ExEXCL 32 Operating MD2 ...
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Section 1 Overview Type Symbol TFP-144V BP-176V TLP-145V I/O Interrupts NMI 11 IRQ15 to 17, IRQ0 50, 85, 84, 135 to 133 ExIRQ15 51 to 58, to 12, 10 ExIRQ6 ETRST* 2 ...
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Type Symbol TFP-144V BP-176V TLP-145V I/O 16-bit timer TCLKA 92 pulse unit TCLKB 91 (TPU) TCLKC 89 TCLKD 87 TIOCA0 94 TIOCB0 93 TIOCC0 92 TIOCD0 91 TIOCA1 90 TIOCB1 89 TIOCA2 88 TIOCB2 87 16-bit cycle TCMCKI3 6, 4, ...
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Section 1 Overview Type Symbol TFP-144V 14-bit PWM PWX0 5 timer PWX1 6 (PWMX) Serial TxD1 133 communi- TxD2 136 cation RxD1 134 interface RxD2 137 (SCI_1, SCK1 135 SCI_2) SCK2 2 Keyboard PS2AC 39 buffer PS2BC 37 control unit ...
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Type Symbol TFP-144V Serial FTxD 16 communic- FRxD 15 ation RI 118 interface DCD with FIFO 117 (SCIF) DSR 116 DTR 115 CTS 114 RTS 113 LPC LAD3 to 124 to Interface LAD0 121 (LPC) LFRAME 125 LRESET 126 LCLK ...
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Section 1 Overview Type Symbol TFP-144V BP-176V TLP-145V I/O A/D AN15 66, converter AN0 AVCC 76 AVref 77 AVSS bus SCL0 14 interface SCL1 135 (IIC) SCL2 55 ExSCLA 53 ...
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Type Symbol TFP-144V BP-176V TLP-145V I/O I/O port P17 to 104 to 110, P10 112 P27 103 P20 P37 to 128 to 121 D7, A8, P30 P47 P40 138 to 136 P52 to ...
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Section 1 Overview Type Symbol TFP-144V BP-176V TLP-145V I/O I/O port PA7 35, PA0 PB7 to 113 to 120 D11, A12, PB0 PC7 PC0 PD7 PD0 ...
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Type Symbol TFP-144V BP-176V TLP-145V I/O PJ7 to PJ0 ⎯ I/O port Notes: 1. Pins PE4 to PE1 are not supported by the system development tool (emulator). 2. Following precautions are required on the power-on reset signal that is applied ...
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Section 1 Overview Rev. 3.00 Sep. 28, 2009 Page 28 of 910 REJ09B0350-0300 ...
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The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU ⎯ 16 ÷ 8-bit register-register divide: 12 states ⎯ 16 × 16-bit register-register multiply: 3 states ⎯ 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode • Power-down ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: • More general registers and control registers ⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the ...
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H'0000 Exception vector 1 H'0001 H'0002 Exception vector 2 H'0003 H'0004 Exception vector 3 H'0005 H'0006 Exception vector 4 H'0007 H'0008 Exception vector 5 H'0009 H'000A Exception vector 6 H'000B Figure 2.1 Exception Vector Table (Normal Mode (16 ...
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Section 2 CPU 2.2.2 Advanced Mode • Address Space Linear access to a 16-Mbyte maximum address space is provided. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers the upper 16-bit ...
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a ...
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...
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Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), an ...
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Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...
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Initial Bit Bit Name Value 1 V Undefined R Undefined R/W 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32- bit registers denoted MACH and MACL. The lower 10 ...
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Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: ...
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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address ...
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Instruction Set The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* LDM, STM MOVFPE* Arithmetic ADD, SUB, CMP, NEG operation ...
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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description Rd General ...
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Symbol Description :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers ( E7), and 32-bit registers (ER0 to ER7). Table 2.3 Data Transfer ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data and ...
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Table 2.4 Arithmetic Operations Instructions (2) 1 Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 ...
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Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ...
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Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
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Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) 1 Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B XORs the carry flag with a specified bit in a general register or memory operand and stores the ...
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Table 2.8 Branch Instructions Instruction Size Function ⎯ Bcc Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE ...
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Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function ⎯ TRAPA Starts trap-instruction exception handling. ⎯ RTE Returns from an exception-handling routine. ⎯ SLEEP Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR LDC ...
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Table 2.10 Block Data Transfer Instructions Instruction Size Function ⎯ if R4L ≠ 0 then EEPMOV.B else next; ⎯ ≠ 0 then EEPMOV.W else next; Transfers a data block. Starting from the address set in ER5, transfers data ...
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Section 2 CPU 2.6.2 Basic Instruction Formats The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field ...
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Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. ...
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Section 2 CPU 2.7.3 Register Indirect with Displacement⎯@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives ...
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Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address Note: Normal mode is not available in this LSI. 2.7.6 Immediate⎯#xx:8, #xx:16, or #xx:32 The ...
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Section 2 CPU 2.7.8 Memory Indirect⎯@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of ...
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Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is ...
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Section 2 CPU Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Note: * Normal mode is not available in this LSI. Rev. 3.00 Sep. 28, 2009 Page 62 of 910 REJ09B0350-0300 Effective Address Calculation ...
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Processing States The H8S/2600 CPU has four main processing states: the reset state, exception handling state, program execution state and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state, the CPU and all on-chip ...
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Section 2 CPU End of exception handling Exception-handling state RES = high *1 Reset state From any state, a transition to the reset state is made whenever the RES pin Notes: 1. goes low. A transition can also be made ...
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Usage Note 2.9.1 Notes on Using the Bit Operation Instruction Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte units after bit operation. Therefore, attention must be paid when these instructions ...
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Section 2 CPU Rev. 3.00 Sep. 28, 2009 Page 66 of 910 REJ09B0350-0300 ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports three operating modes (modes 2, 4, and 6). The operating mode is determined by the setting of the mode pins (MD2 and MD1). Table 3.1 shows the MCU ...
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Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating modes. Table 3.2 Register Configuration Register Name Mode control register System control register Serial timer control register System control register 3 3.2.1 Mode Control ...
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System Control Register (SYSCR) SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables the on-chip RAM address space. ...
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Section 3 MCU Operating Modes Initial Bit Bit Name Value 1 KINWUE 0 0 RAME 1 Rev. 3.00 Sep. 28, 2009 Page 70 of 910 REJ09B0350-0300 R/W Description R/W Keyboard Control Register Access Enable When the RELOCATE bit is cleared ...
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Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Initial Bit Bit Name Value 7 IICX2 0 6 IICX1 0 5 ...
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Section 3 MCU Operating Modes Initial Bit Bit Name Value 3 FLSHE 0 2 IICS 0 1 ICKS1 0 0 ICKS0 0 Rev. 3.00 Sep. 28, 2009 Page 72 of 910 REJ09B0350-0300 R/W Description R/W Flash Memory Control Register Enable ...
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System Control Register 3 (SYSCR3) SYSCR3 selects the register map and interrupt vector. Initial Value Bit Bit Name 7 — EIVS RELOCATE — All 0 Note: * Switch the modes when ...
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Section 3 MCU Operating Modes 3.4 Address Map Figures 3.1 shows the address map in each operating mode. Rev. 3.00 Sep. 28, 2009 Page 74 of 910 REJ09B0350-0300 Mode 2 (EXPE = 0) Advanced mode Single-chip mode ROM: 160 Kbytes ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, illegal instruction, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If ...
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Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to exception sources. Table 4.2 and table 4.3 list the exception sources and their vector addresses. The EIVS bit in the system control register ...
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Exception Source Internal interrupt* Reserved for system use Reserved for system use Reserved for system use External interrupt WUE15 to WUE8 Internal interrupt* External interrupt IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Internal interrupt* Note: * For details on ...
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Section 4 Exception Handling Table 4.3 Exception Handling Vector Table (Extended Vector Mode) Exception Source Reset Reserved for system use Illegal instruction Reserved for system use Direct transition External interrupt (NMI) Trap instruction (four sources) Reserved for system use External ...
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Exception Source Internal interrupt* External interrupt IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Internal interrupt* Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Tables. 4.3 Reset A reset has the ...
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Section 4 Exception Handling Figure 4.1 shows an example of the reset sequence. φ RES Internal address bus Internal read signal Internal write signal Internal data bus (1) Reset exception handling vector address ( H'000000 ( ...
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Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to WUE8) and internal interrupt sources from the on-chip ...
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Section 4 Exception Handling 4.6 Exception Handling by Illegal Instruction The exception handling by the illegal instruction starts when an undefined code is executed. The exception handling by the illegal instruction is always executable in the program execution state. The ...
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Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode SP Notes: * Ignored on return. Normal mode is not available in this LSI. Figure 4.2 ...
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Section 4 Exception Handling 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control ...
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Section 5 Interrupt Controller SYSCR3 SYSCR NMIEG NMI input IRQ input KIN input WUE input Internal interrupt sources WOVI0 to IBFI3 Interrupt controller [Legend] Interrupt control register ICR: IRQ sense control register ISCR: IRQ enable register IER: IRQ status register ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Pin Name I/O NMI Input IRQ15 to IRQ0, Input ExIRQ15 to ExIRQ6 KIN15 to KIN0 Input WUE15 to WUE8 Input Function Nonmaskable external interrupt ...
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Section 5 Interrupt Controller 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). For details on system control register 3 (SYSCR3), see section 3.2.4, ...
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Register Name Wake-up sense control register Wake-up input interrupt status register Wake-up enable register 1. Address in the upper cell: when RELOCATE = 0, address in the lower cell: when Note: RELOCATE = 1 2. Address in the upper cell: ...
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Section 5 Interrupt Controller Table 5.3 Correspondence between Interrupt Source and ICR (H8S/2140B Group Compatible Vector Mode: EIVS = 0) Bit Bit Name ICRA 7 ICRn7 IRQ0 6 ICRn6 IRQ1 5 ICRn5 IRQ2, IRQ3 4 ICRn4 IRQ4, IRQ5 3 ICRn3 ...
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Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE bit are set address break is requested. Bit Bit Name Initial Value 7 CMF Undefined — ...
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Section 5 Interrupt Controller 5.3.3 Break Address Registers (BARA to BARC) The BAR registers specify an address that break address. An address in which the first byte of an instruction exists should be ...
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IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ6. • ISCR16H Bit Bit Name Initial Value R/W 7 IRQ15SCB ...
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Section 5 Interrupt Controller • ISCR16L Bit Bit Name Initial Value 7 IRQ11SCB 0 6 IRQ11SCA 0 5 IRQ10SCB 0 4 IRQ10SCA 0 3 IRQ9SCB 0 2 IRQ9SCA 0 1 IRQ8SCB 0 0 IRQ8SCA 0 • ISCRH Bit Bit Name ...
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ISCRL Bit Bit Name Initial Value 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 R/W Description R/W IRQn Sense Control B R/W IRQn ...
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Section 5 Interrupt Controller 5.3.5 IRQ Enable Registers (IER16, IER) The IER registers enable and disable interrupt requests IRQ15 to IRQ0. • IER16 Bit Bit Name Initial Value 7 IRQ15E 0 6 IRQ14E 0 5 IRQ13E 0 4 IRQ12E 0 ...
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IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. • ISR16 Bit Bit Name Initial Value 7 IRQ15F 0 6 IRQ14F 0 5 IRQ13F 0 4 IRQ12F ...
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Section 5 Interrupt Controller • ISR Bit Bit Name Initial Value 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 IRQ1F 0 0 IRQ0F 0 Note: * Only 0 can ...
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Keyboard Matrix Interrupt Mask Registers (KMIMRA KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR) The KMIMR and WUEMR registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0) and wake-up event interrupt inputs (WUE15 to WUE8). • KMIMRA Bit Bit ...
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Section 5 Interrupt Controller • WUEMR Bit Bit Name Initial Value 7 WUEMR15 1 6 WUEMR14 1 5 WUEMR13 1 4 WUEMR12 1 3 WUEMR11 1 2 WUEMR10 1 1 WUEMR9 1 0 WUEMR8 1 Rev. 3.00 Sep. 28, 2009 ...
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Figure 5.2 shows the relation between the IRQ7 and IRQ6 interrupts, KMIMR, and KMIMRA in H8S/2140B Group compatible vector mode. The relation in extended vector mode is shown in figure 5.3. KMIMR0 (Initial value of 1) P60/KIN0 KMIMR5 (Initial value ...
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Section 5 Interrupt Controller In H8S/2140B Group compatible vector mode, interrupt input from the IRQ7 pin is ignored when even one of the KMIMR15 to KMIMR8 bits is cleared the KIN7 to KIN0 pins or KIN15 to ...
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IRQ Sense Port Select Register 16 (ISSR16) IRQ Sense Port Select Register (ISSR) ISSR16 and ISSR select the IRQ15 to IRQ0 interrupt external input from the IRQ15 to IRQ7 pins and ExIRQ15 to ExIRQ7 pins. • ISSR16 Bit Bit ...
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Section 5 Interrupt Controller 5.3.9 Wake-Up Sense Control Register (WUESCR) Wake-Up Input Interrupt Status Register (WUESR) Wake-Up Enable Register (WER) WUESCR selects the interrupt source of the wake-up event interrupt inputs (WUE15 to WUE8). WUESR is an interrupt request flag ...
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WER Bit Bit Name Initial Value 7 WUEE ⎯ All 0 5.4 Interrupt Sources 5.4.1 External Interrupt Sources The interrupt sources of external interrupts are NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15 to ...
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Section 5 Interrupt Controller When the interrupts are requested while IRQ15 to IRQ0 interrupt requests are generated at low level of IRQn input, hold the corresponding IRQ input at low level until the interrupt handling starts. Then put the relevant ...
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When using the IRQ6 pin as the IRQ6 interrupt input pin, the KMIMR6 bit must be cleared to 0. When using the IRQ7 pin as the IRQ7 interrupt input pin, the KMIMR15 to KMIMR8 bits must all be set ...
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Section 5 Interrupt Controller 5.4.2 Internal Interrupt Sources Internal interrupts issued from the on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually ...
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Origin of Interrupt Source Name — Reserved for system use WDT_0 WOVI0 (Interval timer) WDT_1 WOVI1 (Interval timer) — Address break A/D converter ADI (A/D conversion end) — Reserved for system use External pin WUE15 to WUE8 TPU_0 TGI0A (TGR0A ...
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Section 5 Interrupt Controller Origin of Interrupt Source Name TCM_2 TICI2 (Input capture) TCMI2 (Compare match) TOVMI2 (Cycle overflow) TUDI2 (Cycle underflow) TOVI2 (Overflow) TCM_3 TICI3 (Input capture) TCMI3 (Compare match) TOVMI3 (Cycle overflow) TUDI3 (Cycle underflow) TOVI3 (Overflow) TDP_0 ...
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Origin of Interrupt Source Name TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match B) OVI0 (Overflow) — Reserved for system use TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) — Reserved for system use TMR_X CMIAY (Compare ...
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Section 5 Interrupt Controller Origin of Interrupt Source Name PS2 KBIA (Reception completion A) KBIB (Reception completion B) KBIC (Reception completion C) KBTIA (Transmission completion A)/ KBCA (1st KCLKA) KBTIB (Transmission completion B)/ KBCB (1st KCLKB) KBTIC (Transmission completion C)/ ...
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Table 5.6 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode) Origin of Interrupt Source Name External pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 — Reserved for system use WDT_0 WOVI0 (Interval timer) WDT_1 WOVI1 (Interval ...
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Section 5 Interrupt Controller Origin of Interrupt Source Name TPU_2 TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TGI2V (Overflow 1) TGI2U (Underflow 2) — Reserved for system use TCM_0 TICI0 (Input capture) TCMI0 (Compare match) TOVMI0 (Cycle ...
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Origin of Interrupt Source Name TDP_2 TICI2 (Input capture) TCMI2 (Compare match) TPDMXI2 (Cycle overflow) TPDMNI2 (Cycle underflow) TWDMNI2 (Pulse width lower limit underflow) TWDMXI2 (Pulse width upper limit overflow) TOVI2 (Overflow) — Reserved for system use External IRQ8 pin ...
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Section 5 Interrupt Controller Origin of Interrupt Source Name SCI_2 ERI2 (Reception error) RXI2 (Reception completion) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) IIC_0 IICI0 (1-byte transmission/reception completion) ⎯ Reserved for system use IIC_1 IICI1 (1-byte transmission/reception completion) ...
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Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI and address break interrupts are always accepted except ...
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Section 5 Interrupt Controller (1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control ...
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Table 5.9 shows operations and control signal functions in each interrupt control mode. Table 5.9 Operations and Control Signal Functions in Each Interrupt Control Mode Setting Interrupt Control Mode INTM1 INTM0 [Legend] Ο: Interrupt operation ...
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Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. An ...
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Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than NMI and address break by comparing the I and UI bits in CCR in the CPU, and the ...
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Section 5 Interrupt Controller Figure 5.9 shows a flowchart of the interrupt acceptance operation interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. 2. ...
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An interrupt with interrupt control level 1? IRQ0 Yes Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 Program execution state Interrupt generated? Yes Yes NMI No No Yes No IRQ0 No Yes IRQ1 Yes ...
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Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.10 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...
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Interrupt Response Times Table 5.10 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 5.10 Interrupt Response Times No. Execution Status 1 Interrupt ...
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Section 5 Interrupt Controller 5.7 Address Breaks 5.7.1 Features With this LSI possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an ...
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Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the ...
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Section 5 Interrupt Controller • Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction fetch fetch φ Address bus H'0310 H'0312 H'0314 H'0316 NOP execution Break request signal H'0310 NOP H'0312 NOP H'0314 NOP H'0316 ...
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Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to ...
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Section 5 Interrupt Controller 5.8.2 Instructions for Disabling Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. ...
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External Interrupt Pin in Software Standby Mode and Watch Mode • When the pins (IRQ15 to IRQ0, ExIRQ15 to ExIRQ6, KIN15 to KIN0, and WUE15 to WUE8) are used as external input pins in software standby mode or watch ...
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Section 5 Interrupt Controller Rev. 3.00 Sep. 28, 2009 Page 132 of 910 REJ09B0350-0300 ...
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Section 6 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an on-chip bus controller (BSC). Considering the software compatibility with similar products, you must be careful to set appropriate values to ...
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Section 6 Bus Controller (BSC) 6.1.2 Wait State Control Register (WSCR) Initial Bit Bit Name Value 7, 6 — All 1 5 ABW 1 4 AST 1 3 WMS1 0 2 WMS0 0 1 WC1 1 0 WC0 1 Rev. ...
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Table 7.1 lists the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a ...
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Section 7 I/O Ports Table 7.1 Port Functions Port Description Bit I/O Port 1 General I/O 7 P17 port 6 P16 5 P15 4 P14 3 P13 2 P12 1 P11 0 P10 Port 2 General I/O 7 P27 port ...
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Port Description Bit I/O Port 4 General I/O 7 P47 port also functioning as 6 P46 PWMX and 5 P45 PWMU_B outputs, TCM input, and 4 P44 TMR_0, 3 P43/SCK2 TMR_1, IIC_1, and SCI_2 2 P42/SDA1 inputs/outputs 1 P41 0 ...
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Section 7 I/O Ports Port Description Bit I/O ⎯ Port 7 General input 7 port also ⎯ 6 functioning as ⎯ 5 A/D converter analog input ⎯ 4 ⎯ 3 ⎯ 2 ⎯ 1 ⎯ 0 Port 8 General I/O ...
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Port Description Bit I/O Port A General I/O 7 PA7/PS2CD port also 6 PA6/PS2CC functioning as keyboard 5 PA5/PS2BD input and 4 PA4/PS2BC PS2 input/output 3 PA3/PS2AD 2 PA2/PS2AC 1 PA1/PS2DD 0 PA0/PS2DC Port B General I/O 7 PB7 port ...
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Section 7 I/O Ports Port Description Bit I/O Port D General I/O 7 PD7 port also 6 PD6 functioning as A/D converter 5 PD5 analog input 4 PD4 3 PD3 2 PD2 1 PD1 0 PD0 ⎯ Port E General ...
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Port Description Bit I/O PG7/ExSCLB ExIRQ15 Port G General I/O 7 port also PG6/ExSDAB ExIRQ14 6 functioning as PG5/ExSCLA ExIRQ13 interrupt and 5 TDP inputs, PG4/ExSDAA ExIRQ12 4 TMR_X and TMR_Y 3 PG3/SCL2 inputs, and 2 PG2/SDA2 IIC0 to IIC2 ...
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Section 7 I/O Ports Port Description Bit I/O 2 Port J General I/O 7 PJ7* port 2 6 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0* Notes: 1. Not ...
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Register Descriptions Table 7.2 lists each port registers. Table 7.2 Register Configuration in Each Port Number Port of Pins DDR DR Port Port Port Port 4 8 ...
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Section 7 I/O Ports 7.1.1 Data Direction Register (PnDDR and DDR specifies the port input or output for each bit. The upper five bits in P5DDR, the ...
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Data Register (PnDR and register that stores output data of the pins to be used as the general output port. Since the P96DR bit is determined by the state ...
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Section 7 I/O Ports 7.1.4 Pull-Up MOS Control Register (PnPCR and J) Pull-Up MOS Control Register (KMPCR) (Port 6) PCR is a register that controls on/off of the port ...
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Table 7.3 Input Pull-Up MOS State (1) • Port and J Port Pin State Port 1 Port output Port input Port 2 Port output Port input Port 3 Port output Port input Port 6 Port ...
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Section 7 I/O Ports Table 7.3 Input Pull-Up MOS State (2) • Port and H Port Pin State Port B Port output Port input Port C Port output Port input Port D Port output Port input ...
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Output Data Register (PnODR and 7.1.5 ODR is a register that stores output data for ports. The upper two bits in PHODR are reserved. Bit Bit Name Initial Value 7 Pn7ODR 0 ...
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Section 7 I/O Ports Noise Canceller Decision Control Register (PnNCMC and G) 7.1.7 NCMC controls whether expected for the input signal to port n pins in bit units. Bit Bit Name Initial ...
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Sampling clock selection t Pin Latch Latch input t Sampling clock Figure 7.1 Noise Cancel Circuit P6n input PCn input PGn input 1 expected P6n input PCn input PGn input 0 expected ...
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Section 7 I/O Ports Port Nch-OD Control Register (PnNOCR and 7.1.9 The individual bits of NOCR specify output driver type for the pins of port n that is specified as output. The upper ...
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Pin Functions The pin function is switched according to the setting of the PORTS bit in PTCNT2. (Ports and H) PORTS = 0 (1) DDR NOCR ODR 0 N-ch. driver P-ch. driver Input pull-up Off ...
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Section 7 I/O Ports 7.2 Output Buffer Control This section describes the output priority of each pin. The name of each peripheral module pin is followed by “_OE”. This (for example: TIOCA4_OE) indicates whether the output of the corresponding function ...