DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 38

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6 Usage Notes ....................................................................................................................... 352
Section 13 8-Bit Timer (TMR)..........................................................................355
13.1 Features.............................................................................................................................. 355
13.2 Input/Output Pins............................................................................................................... 358
13.3 Register Descriptions ......................................................................................................... 359
13.4 Operation ........................................................................................................................... 374
13.5 Operation Timing............................................................................................................... 375
13.6 TMR_0 and TMR_1 Cascaded Connection....................................................................... 379
13.7 TMR_Y and TMR_X Cascaded Connection ..................................................................... 380
Rev. 3.00 Sep. 28, 2009 Page xxxvi of xliv
REJ09B0350-0300
12.6.1 Conflict between TDPCNT Write and Count-Up Operation ................................ 352
12.6.2 Conflict between TDPPDMX Write and Compare Match.................................... 352
12.6.3 Conflict between Input Capture and TDPICR Read ............................................. 353
12.6.4 Conflict between Edge Detection in Cycle Measurement Mode and
12.6.5 Conflict between Edge Detection in Cycle Measurement Mode and
12.6.6 Settings for TDPCKI and TDPMCI...................................................................... 354
12.6.7 Setting for Module Stop Mode ............................................................................. 354
13.3.1 Timer Counter (TCNT)......................................................................................... 360
13.3.2 Time Constant Register A (TCORA).................................................................... 361
13.3.3 Time Constant Register B (TCORB) .................................................................... 361
13.3.4 Timer Control Register (TCR).............................................................................. 362
13.3.5 Timer Control/Status Register (TCSR)................................................................. 366
13.3.6 Time Constant Register C (TCORC) .................................................................... 371
13.3.7 Input Capture Registers R and F (TICRR and TICRF)......................................... 371
13.3.8 Timer Connection Register I (TCONRI) .............................................................. 372
13.3.9 Timer Connection Register S (TCONRS) ............................................................ 372
13.3.10 Timer XY Control Register (TCRXY) ................................................................. 373
13.4.1 Pulse Output.......................................................................................................... 374
13.5.1 TCNT Count Timing ............................................................................................ 375
13.5.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 376
13.5.3 Timing of Timer Output at Compare-Match......................................................... 376
13.5.4 Timing of Counter Clear at Compare-Match........................................................ 377
13.5.5 TCNT External Reset Timing............................................................................... 377
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 378
13.6.1 16-Bit Count Mode ............................................................................................... 379
13.6.2 Compare-Match Count Mode ............................................................................... 379
13.7.1 16-Bit Count Mode ............................................................................................... 380
13.7.2 Compare-Match Count Mode ............................................................................... 380
Writing to the Upper Limit or Lower Limit Register ........................................... 353
TDPMDS Bit Clearing.......................................................................................... 354