DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 426
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
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Quantity:
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Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
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- Current page: 426 of 960
- Download datasheet (6Mb)
Section 13 8-Bit Timer (TMR)
13.7
If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode
can be selected by the settings of the CKSX and CKSY bits in TCRXY.
13.7.1
When bits CKS2 to CKS0 in TCR_Y are set to B'100 and the CKSY bit in TCRXY is set to 1, the
timer functions as a single 16-bit timer with TMR_Y occupying the upper eight bits and TMR_X
occupying the lower 8 bits.
• Setting of compare-match flags
• Counter clear specification
• Pin output
13.7.2
When bits CKS2 to CKS0 in TCR_X are set to B'100 and the CKSX bit in TCRXY is set to 1,
TCNT_X counts the occurrence of compare-match A for TMR_Y. TMR_X and TMR_Y are
controlled independently. Conditions such as setting of the CMF flag, generation of interrupts,
output from the TMO pin, and counter clearing are in accordance with the settings for each
channel.
Rev. 3.00 Sep. 28, 2009 Page 380 of 910
REJ09B0350-0300
⎯ The CMF flag in TCSR_Y is set to 1 when an upper 8-bit compare-match occurs.
⎯ The CMF flag in TCSR_X is set to 1 when a lower 8-bit compare-match occurs.
⎯ If the CCLR1 and CCLR0 bits in TCR_Y have been set for counter clear at compare-
⎯ The settings of the CCLR1 and CCLR0 bits in TCR_X are enabled, and the lower 8 bits of
⎯ Control of output from the TMOY pin by bits OS3 to OS0 in TCSR_Y is in accordance
⎯ Control of output from the TMOX pin by bits OS3 to OS0 in TCSR_X is in accordance
match, only the upper eight bits of TCNT_Y are cleared. The upper eight bits of TCNT_Y
are also cleared when counter clear by the TMRIY pin has been set.
TCNT_X can be cleared by the counter.
with the upper 8-bit compare-match conditions.
with the lower 8-bit compare-match conditions.
TMR_Y and TMR_X Cascaded Connection
16-Bit Count Mode
Compare-Match Count Mode
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