DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 635

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This LSI has an on-chip LPC interface.
The LPC includes four register sets, each of which comprises data and status registers, control
register, the fast Gate A20 logic circuit, and the host interrupt request circuit.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data and one for host interrupt requests. This LPC
module supports I/O read and I/O write cycle transfers. It is also provided with power-down
functions that can control the PCI clock and shut down the LPC interface.
19.1
• Supports LPC interface I/O read and I/O write cycles
• Four register sets comprising data and status registers
• Supports SCIF
• Supports SERIRQ
⎯ Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
⎯ Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
⎯ The basic register set comprises three bytes: an input register (IDR), output register (ODR),
⎯ I/O addresses from H'0000 to H'FFFF are selected for channels 1 to 4.
⎯ A fast Gate A20 function is provided for channel 1.
⎯ For channel 3, sixteen bidirectional data register bytes can be manipulated in addition to
⎯ The LPC interface is connected to the SCIF, allowing direct control of the SCIF by the
⎯ Host interrupt requests are transferred serially on a single signal line (SERIRQ).
⎯ On channel 1, HIRQ1 and HIRQ12 can be generated.
⎯ On channels 2, 3 and 4, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
⎯ In the SCIF, HIRQ1, SMI, and HIRQ3 to HIRQ15 can be generated.
⎯ Operation can be switched between quiet mode and continuous mode.
⎯ The CLKRUN signal can be manipulated to restart the PCI clock (LCLK).
and status register (STR).
the basic register set.
LPC host.
Features
Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 589 of 910
Section 19 LPC Interface (LPC)
REJ09B0350-0300