DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 535

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4.2
Figure 16.2 illustrates the typical format for asynchronous serial communication. One frame
consists of a start bit (low level), followed by transmit/receive data (LSB-first: from the least
significant bit), a parity bit, and a stop bit (high level). In asynchronous serial communication, the
transmission line is usually held high in the mark state (high level). The SCIF monitors the
transmission line, and when it detects the space state (low level), recognizes a start bit and starts
serial communication. Inside the SCIF, the transmitter and receiver are independent units,
enabling full-duplex communication. Both of the transmitter and receiver also have a 16-stage
FIFO buffered structure so that data can be read or written during transmission or reception,
enabling continuous data transmission and reception.
Serial data
Operation in Asynchronous Communication
1
Figure 16.2 Data Format in Serial Transmission/Reception
Start
1 bit
bit
0
(Example with 8-Bit Data, Parity and 2 Stop Bits)
D0
D1
One unit of transfer data (character or frame)
D2
Transmit/receive data
5, 6, 7, or 8 bits
D3
Section 16 Serial Communication Interface with FIFO (SCIF)
D4
D5
D6
Rev. 3.00 Sep. 28, 2009 Page 489 of 910
D7
Idle state (mark state)
Parity
none
1 bit
0/1
bit
or
1
Stop bit
1, 1.5,
2 bits
or
1
REJ09B0350-0300
1