DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 759
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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The procedures for download of the on-chip program, initialization, and erasing are shown in
figure 22.13.
The procedure program must be executed in an area other than the user MAT to be erased. Setting
the SCO bit in FCCS to 1 to request download must be executed in the on-chip RAM. The area
that can be executed in the steps of the procedure program (on-chip RAM and user MAT) is
shown in section 22.8.4, Storable Areas for On-Chip Program and Program Data. For the
downloaded on-chip program area, see figure 22.11.
Erasing Procedure in User Program Mode
Set SCO to 1 and execute
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
destination by FTDAR
Start erasing procedure
specify download
Set FKEY to H'A5
Set the FPEFEQ
Clear FKEY to 0
Initialization
FPFR = 0 ?
DPFR = 0?
parameter
download
program
1
Yes
Yes
Figure 22.13 Erasing Procedure in User Program Mode
Initialization error processing
Download error processing
No
No
1.
No
JSR FTDAR setting + 16
Rev. 3.00 Sep. 28, 2009 Page 713 of 910
Disable interrupts and
bus master operation
Set FEBS parameter
procedure program
Clear FKEY to 0
Set FKEY to H'5A
other than CPU
Required block
End erasing
FPFR = 1 ?
completed?
erasing is
Erasing
1
Yes
Yes
Section 22 Flash Memory
Clear FKEY and erasing
No
error processing
REJ09B0350-0300
2.
3.
4.
5.
6.
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