DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 125
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 125 of 960
- Download datasheet (6Mb)
Note: *
4.3
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20
ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A
reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The
chip can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog
Timer (WDT).
4.3.1
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized
2. The reset exception handling vector address is read and transferred to the PC, and then
Exception Source
Internal interrupt*
External interrupt IRQ8
Internal interrupt*
and the I bit in CCR is set to 1.
program execution starts from the address indicated by the PC.
Reset
Reset Exception Handling
For details on the internal interrupt vector table, see section 5.5, Interrupt Exception
Handling Vector Tables.
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
Vector
Number
34
55
56
57
58
59
60
61
62
63
64
127
⎜
⎜
Rev. 3.00 Sep. 28, 2009 Page 79 of 910
Vector Addresses
Normal Mode
H'000088 to H'00008B
H'0000DC to H'0000DF
H'0000E0 to H'0000E3
H'0000E4 to H'0000E7
H'0000E8 to H'0000EB
H'0000EC to H'0000EF
H'0000F0 to H'0000F3
H'0000F4 to H'0000F7
H'0000F8 to H'0000FB
H'0000FC to H'0000FF
H'000100 to H'000103
H'0001FC to H'0001FF
Section 4 Exception Handling
⎜
⎜
REJ09B0350-0300
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