AT90USB1287-AU Atmel, AT90USB1287-AU Datasheet - Page 274

• Manufacturer Part Number: AT90USB1287-AU
• Description: IC AVR MCU 128K 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB1287-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR USB
• No. Of I/o's: 48
• Eeprom Memory Size: 4KB
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT90USB1287-16AU; AT90USB1287-16AU

22.13.2
22.13.2.1
274
AT90USB64/128
Detailed description
switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in accor-
dance with the status of the new bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
read data from the bank, and cleared by hardware when the bank is empty.
The data are read by the CPU, following the next flow:
If the endpoint uses 2 banks, the second one can be filled by the HOST while the current one is
being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already
ready and RXOUTI is set immediately.
• When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled
• The CPU acknowledges the interrupt by clearing RXOUTI,
• The CPU can read the number of byte (N) in the current bank (N=BYCT),
• The CPU can read the data from the current bank (“N” read of UEDATX),
• The CPU can free the bank by clearing FIFOCON when all the data is read, that is:
(RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending
on the software architecture,
– after “N” read of UEDATX,
– as soon as RWAL is cleared by hardware.
Example with 1 OUT data bank
RXOUTI
RXOUTI
FIFOCON
FIFOCON
Example with 2 OUT data banks
OUT
OUT
(to bank 0)
(to bank 0)
DATA
DATA
HW
HW
ACK
ACK
SW
SW
read data from CPU
OUT
BANK 0
NAK
read data from CPU
BANK 0
(to bank 1)
DATA
SW
OUT
ACK
(to bank 0)
DATA
HW
SW
HW
ACK
SW
read data from CPU
BANK 1
SW
read data from CPU
BANK 0
7593K–AVR–11/09