AT90USB1287-AU Atmel, AT90USB1287-AU Datasheet - Page 338

• Manufacturer Part Number: AT90USB1287-AU
• Description: IC AVR MCU 128K 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB1287-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR USB
• No. Of I/o's: 48
• Eeprom Memory Size: 4KB
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT90USB1287-16AU; AT90USB1287-16AU

27. IEEE 1149.1 (JTAG) Boundary-scan
27.1
27.2
27.3
338
Features
System Overview
Data Registers
AT90USB64/128
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The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by
the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to
drive values at their output pins, and observe the input values received from other devices. The
controller compares the received data with the expected result. In this way, Boundary-scan pro-
vides a mechanism for testing interconnections and integrity of components on Printed Circuits
Boards by using the four TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-
LOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be
used for testing the Printed Circuit Board. Initial scanning of the Data Register path will show the
ID-Code of the device, since IDCODE is the default JTAG instruction. It may be desirable to
have the AVR device in reset during test mode. If not reset, inputs to the device may be deter-
mined by the scan operations, and the internal software may be in an undetermined state when
exiting the test mode. Entering reset, the outputs of any port pin will instantly enter the high
impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction
can be issued to make the shortest possible scan chain through the device. The device can be
set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET
instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST
instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins during normal operation of the part.
The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR must be
cleared to enable the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher
than the internal chip frequency is possible. The chip clock is not required to run.
The Data Registers relevant for Boundary-scan operations are:
• Bypass Register
• Device Identification Register
• Reset Register
• Boundary-scan Chain
JTAG (IEEE std. 1149.1 compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections
Supports the Optional IDCODE Instruction
Additional Public AVR_RESET Instruction to Reset the AVR
7593K–AVR–11/09