AT90USB1287-AU Atmel, AT90USB1287-AU Datasheet - Page 360

• Manufacturer Part Number: AT90USB1287-AU
• Description: IC AVR MCU 128K 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB1287-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR USB
• No. Of I/o's: 48
• Eeprom Memory Size: 4KB
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT90USB1287-16AU; AT90USB1287-16AU

28.7.9
28.7.10
360
AT90USB64/128
Reading the Fuse and Lock Bits from Software
Reading the Signature Row from Software
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an (E)LPM
instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in
SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and
SPMEN bits will auto-clear upon completion of reading the Lock bits or if no (E)LPM instruction
is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles.
When BLBSET and SPMEN are cleared, (E)LPM will work as described in the Instruction set
Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SPMEN bits in SPMCSR. When an (E)LPM instruction is executed within three cycles after
the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will
be loaded in the destination register as shown below. Refer to
detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an (E)LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
shown below. Refer to
High byte.
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an (E)LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,
the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown
below. Refer to
Fuse byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in
LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set in
SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and
SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM
instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will
work as described in the Instruction set Manual
Bit
Rd
Bit
Rd
Bit
Rd
Bit
Rd
Table 28-6 on page 361
7
–
7
FLB7
7
FHB7
7
–
Table 29-3 on page 367
6
–
6
FLB6
6
FHB6
6
–
Table 29-4 on page 368
5
BLB12
5
FLB5
5
FHB5
5
–
and set the SIGRD and SPMEN bits in SPMCSR. When an
4
FLB4
4
FHB4
4
–
4
BLB11
for detailed description and mapping of the Extended
3
BLB02
3
FLB3
3
FHB3
3
–
for detailed description and mapping of the Fuse
2
BLB01
2
FLB2
2
FHB2
2
EFB2
1
LB2
1
FLB1
1
FHB1
1
EFB1
Table 29-5 on page 368
0
LB1
0
FLB0
0
FHB0
0
EFB0
7593K–AVR–11/09
for a