AT90USB1287-AU Atmel, AT90USB1287-AU Datasheet - Page 455

• Manufacturer Part Number: AT90USB1287-AU
• Description: IC AVR MCU 128K 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB1287-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR USB
• No. Of I/o's: 48
• Eeprom Memory Size: 4KB
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT90USB1287-16AU; AT90USB1287-16AU

19 USART in SPI Mode ............................................................................. 206
20 2-wire Serial Interface .......................................................................... 216
21 USB controller ...................................................................................... 246
7593K–AVR–11/09
18.1 Overview ............................................................................................................181
18.2 Clock Generation ...............................................................................................182
18.3 Frame Formats ..................................................................................................185
18.4 USART Initialization ...........................................................................................187
18.5 Data Transmission – The USART Transmitter ..................................................188
18.6 Data Reception – The USART Receiver ...........................................................190
18.7 Asynchronous Data Reception ..........................................................................194
18.8 Multi-processor Communication Mode ..............................................................197
18.9 USART Register Description .............................................................................198
18.10 Examples of Baud Rate Setting .......................................................................203
19.1 Overview ............................................................................................................206
19.2 Clock Generation ...............................................................................................207
19.3 SPI Data Modes and Timing ..............................................................................207
19.4 Frame Formats ..................................................................................................208
19.5 Data Transfer .....................................................................................................210
19.6 USART MSPIM Register Description ................................................................212
19.7 AVR USART MSPIM vs. AVR SPI ....................................................................214
20.1 Features ............................................................................................................216
20.2 2-wire Serial Interface Bus Definition ................................................................216
20.3 Data Transfer and Frame Format ......................................................................217
20.4 Multi-master Bus Systems, Arbitration and Synchronization .............................220
20.5 Overview of the TWI Module .............................................................................221
20.6 TWI Register Description ...................................................................................224
20.7 Using the TWI ....................................................................................................227
20.8 Transmission Modes .........................................................................................231
20.9 Multi-master Systems and Arbitration ................................................................244
21.1 Features ............................................................................................................246
21.2 Block Diagram ...................................................................................................246
21.3 Typical Application Implementation ...................................................................247
21.4 General Operating Modes .................................................................................251
21.5 Power modes .....................................................................................................255
21.6 Speed Control ....................................................................................................256
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